Security core using soft key

• US 8,612,772 B1
• Filed: 07/20/2006
• Issued: 12/17/2013
• Est. Priority Date: 09/10/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin, Schleicher, James G. II
• Primary Examiner(s): Yalew, Fikremariam A
• Application Number:
  US11/490,764
• Time in Patent Office: 2,707 Days
• Field of Search: 713/168, 713/189, 713/190, 726/34
• US Class Current: 713/190
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Implementing a key and a protection circuit in a configurable device. A soft key associated with a protection circuit is combined with a user'"'"'s electronic design in generating configuration data for download onto the configurable device. The placement and routing of the soft key is pseudo-randomly arranged with respect to the user'"'"'s electronic design such that its placement and routing on the configurable device is substantially different for binary configuration data that is generated. Hiding the soft key and its connections to the protection circuit and assisting in protecting user electronic designs is achieved.

Claims

1. A method comprising:

receiving a user electronic design;

receiving an assignment to add a protection circuit to the user electronic design;

receiving a first key associated with the protection circuit, wherein the protection circuit is used to perform a comparison between a result generated by using the first key with the protection circuit and a result generated by using a second key with a secure device;

combining, via a processor, the first key with the user electronic design in forming a combined design as soft logic on a configurable device including an integrated circuit; and

generating configurable data for programming the configurable device with the combined design.

2. The method of claim 1, further comprising:

generating a flattened netlist of the user electronic design.

3. The method of claim 2, further comprising:

generating at least one core that contains the first key.

4. The method of claim 3, wherein the at least one core also contains an aspect of the protection circuit for facilitating connections between the first key and the protection circuit.

5. The method of claim 4, wherein the aspect of the protection circuit is selected from the group consisting of a location and a port of the protection circuit.

6. The method of claim 3, wherein the at least one core is encrypted.

7. The method of claim 3, wherein combining the first key with the user electronic design comprises:

inserting the at least one core to the flattened netlist of the user electronic design in forming the combined design.

8. The method of claim 7, wherein inserting at least one core to the flattened netlist of the user electronic design comprises generating a gate level representation of the protection circuit that is usable to combine with the flattened netlist.

9. The method of claim 3, further comprising:

performing placement and routing on the combined design.

10. The method of claim 9, wherein performing placement comprises:

identifying at least one core for obfuscation; and

obfuscating an arrangement of the first key within the user electronic design, the arrangement being associated with at least one storage location within the configurable device.

11. The method of claim 10, wherein identifying the at least one core for obfuscation comprises:

identifying a flag associated with the at least one core.

12. The method of claim 10, wherein obfuscating the arrangement of the first key within the user electronic design comprises:

pseudo randomly assigning a first storage location for the first key.

13. The method of claim 12, wherein obfuscating the arrangement of the first key within the user electronic design comprises:

pseudo randomly assigning a second storage location for the first key.

14. The method of claim 13, wherein the first and second storage locations are look-up tables (LUTs) in a soft logic portion of the configurable device.

15. The method of claim 9, wherein performing routing comprises:

generating interconnects between LUTs and the protection circuit.

16. The method of claim 15, wherein performing routing comprises:

obfuscating an input for the first key on the protection circuit.

17. The method of claim 16, wherein obfuscating an input for the first key on the protection circuit comprises:

routing a first interconnect to a first input port of the protection circuit, the first input port being a decoy receiver of the first key; and

routing a second interconnect to a second input port of the protection circuit, the second input port being an actual receiver of the first key.

18. The method of claim 1, wherein the protection circuit comprises an encryption core for which the first key is a corresponding encryption algorithm unlocking/decoding value.

19. The method of claim 1, wherein the protection circuit comprises a sequence generator for which the first key is a corresponding seed value.

20. The method of claim 1, wherein the protection circuit comprises a sequence generator for which the first key is a corresponding incremental value.

21. The method of claim 1, wherein the protection circuit comprises a comparator.

22. The method of claim 1, wherein the protection circuit is implemented on a hard logic portion of the configurable device.

23. The method of claim 1, wherein the configurable device is a programmable logic device.

24. A method comprising:

powering up a configurable device including an integrated circuit, the configurable device being coupled to a secure device;

programming the configurable device with configurable data, wherein the configurable data is generated from a process that includes;

receiving a user electronic design;

receiving an assignment to add a protection circuit to the user electronic design;

receiving a first key associated with the protection circuit, wherein the protection circuit is used to perform a comparison between a result generated by using the first key with the protection circuit and a result generated by using a second key with a secure device;

combining, via a processor, the first key with the user electronic design in forming a combined design as soft logic within the configurable device; and

generating the configurable data with the combined design;

accessing the first key; and

authenticating the first key with the secure device.

25. The method of claim 24, further comprising:

performing placement and routing on the combined design.

26. The method of claim 25, wherein performing placement comprises:

obfuscating an arrangement of the first key within the user electronic design, the arrangement being associated with at least one storage location within the configurable device.

27. The method of claim 26, wherein obfuscating the arrangement of the key within the user electronic design comprises:

pseudo randomly assigning a storage location for the first key.

28. The method of claim 27, wherein the storage location is a look-up table (LUT) in a soft logic portion of the configurable device.

29. A system, comprising:

a configurable device including a first key that is combined with a user electronic design and implemented as soft logic on the configurable device;

a protection circuit having a first encryption core, said protection circuit being implemented on said configurable device and arranged to return a first result of said first key operating on said first encryption core;

a configuration block implemented on said configurable device, said configuration block including binary configuration data for said user electronic design;

a secure device including a second key implemented as hard logic on the secure device and a second encryption core that is identical to the first encryption core, said secure device being external to the configurable device and being arranged to return a second result of said second key operating on said second encryption core; and

a communication link between said configurable device and said secure device arranged to transmit said second result of said secure device to said protection circuit.

30. The system of claim 29, wherein the protection circuit is implemented as hard logic on the configurable device.