Power management apparatus and methods

• US 8,612,779 B2
• Filed: 07/22/2010
• Issued: 12/17/2013
• Est. Priority Date: 07/22/2009
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Wolfson Microelectronics plc (Cirrus Logic Incorporated)
• Inventors: More, Grant M., Haiplik, Holger
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US12/841,515
• Publication Number:
  US 20110022859A1
• Time in Patent Office: 1,244 Days
• Field of Search: 713/300, 713/320
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

Power management integrated circuits (PMICs) and related methods. In one aspect a PMIC which is operable to provide a plurality of PMIC power states is arranged to provide a predetermined delay before a power state transition. The delay is applied after receipt by the PMIC control circuitry of a power state transition command. Applying a delay allows time for the system powered by the PMIC to perform any necessary shut-down procedures and terminate active processes before power is removed, preventing corruption of the system. The delay is preferably configurable. The PMIC may also be arranged to control power converters which are external to the PMIC. In another aspect the PMIC has translation circuitry for providing the control settings of one power block, e.g. power converter, with any necessary modifications to be used by another power block. This means that only one set of control settings needs to be updated to change the output of both power blocks simultaneously.

Claims

1. A power management integrated circuit being operable, in use, to provide a plurality of power states, wherein the power management integrated circuit is configured to transition from a present power state to another power state in response to a power state transition command, and wherein the power management integrated circuit is arranged to provide a predetermined delay between receipt of a power state transition command and start of the appropriate power state transition, wherein the power management integrated circuit is configured to receive at least some power state transition commands from an operating system of a host device and to apply said predetermined delay in response to a power state transition command received from said operating system, wherein the duration of the predetermined delay is configurable.

2. A power management integrated circuit as claimed in claim 1 wherein the power management integrated circuit is arranged, on receipt of a power transition command, to send a power transition indication signal to at least one output.

3. A power management integrated circuit as claimed in claim 2 wherein the power transition indication signal is an interrupt signal for a device processor.

4. A power management integrated circuit as claimed in claim 1 wherein the predetermined delay is within a range of 1 ms-10 s inclusive.

5. A power management integrated circuit as claimed in claim 1 wherein the duration of the delay is based on a delay setting and wherein the power management integrated circuit is adapted to update the delay setting in response to an appropriate command input.

6. A power management integrated circuit as claimed in claim 1 comprising, or adapted to communicate with, a sequencer for controlling power blocks involved in a power state transition sequence wherein the power management integrated circuit is adapted to implement the predetermined delay prior to initializing said sequencer.

7. A power management integrated circuit as claimed in claim 1 comprising, or adapted to communicate with, a sequencer for controlling power blocks involved in a power state transition sequence wherein at least part of the delay is provided by reserving a plurality of time slots of the sequencer as inactive.

8. A power management integrated circuit as claimed in claim 1 wherein the power management integrated circuit applies the predetermined delay on receipt of any power state transition command.

9. A power management integrated circuit as claimed in claim 1 adapted to, on power up of the power management integrated circuit, to set the duration of the predetermined delay based on a setting in a non-volatile memory.

10. A power management integrated circuit as claimed in claim 1 comprising control circuitry configurable to control at least one power block external to the power management integrated circuit and output power block control signals to at least one power block control output.

11. A power management integrated circuit as claimed in claim 10 wherein the control circuitry for controlling at least one external power block comprises sequencing circuitry for activating or deactivating the power blocks in a specified sequence in a transition from one power state to a different power state.

12. A power management integrated circuit as claimed in claim 10 wherein the control circuitry comprises circuitry to provide control over the configuration settings of the at least one power block external to the power management integrated circuit.

13. A device comprising a power management integrated circuit as claimed in claim 10 and at least one additional power block external to the power management integrated circuit, the additional power block being connected to a power block control output interface.

14. A device as claimed in claim 13 comprising two or more additional power blocks integrated together.

15. A device as claimed in claim 13 wherein said power management integrated circuit is a first power management integrated circuit and the device comprising an additional power management integrated circuit arranged as a slave to the first power management integrated circuit.

16. A device comprising a power management integrated circuit as claimed in claim 1 and a processor, wherein the power management integrated circuit is adapted to, on receipt of a power state transition command that does not originate from the processor, to send a power state change notification signal to the processor.

17. A device as claimed in claim 16 wherein the processor is adapted, on receipt of said power state change signal, to terminate any active processes and/or prevent start of processes not related to a power state transition.

18. A device comprising a power management integrated circuit as claimed in claim 1 and a processor, wherein the predetermined delay applied varies according to processor usage at the time of receipt of a power state transition command.

19. A device as claimed in claim 18 wherein the delay applied is based on a delay setting that is updated by the processor based on usage.

24. A device comprising a power management integrated circuit according to claim 1.

25. A device according to claim 24 wherein the device is a portable electronic device.

26. A device according to claim 24 wherein the device is at least one of:

a computing device;

a laptops;

a notebook computer;

a PDA;

a media players;

an MP3 player;

a video player;

a portable television device;

a communication device;

a mobile telephone;

a mobile email device;

GPS devices or a navigation device.

27. A power management integrated circuit as claimed in claim 1 where the power management integrated circuit is configured to receive at least some power state transition commands from a device processor and to apply said predetermined delay in response to a power state transition command received from said device processor.

20. A power management integrated circuit for managing power supply to a device, the integrated circuit being operable, in use, to provide a plurality of power states, wherein the integrated circuit is configured to transition from a current power state to another power state in response to a power state transition command, and wherein the integrated circuit is configurable so that a predetermined delay can be applied between receipt of a power state transition command and start of the appropriate power state transition, and wherein the integrated circuit is also configurable so that no delay is applied between receipt of a power state transition command and start of the appropriate power transition, and wherein the integrated circuit is configured to receive at least some power state transition commands from an operating system of a host device and is configurable to apply said predetermined delay in response to a power state transition command received from said operating system.

21. A method of performing a power state transition in a device comprising the steps of:

receiving in a power management integrated circuit of the device a power state transition command from an operating system of the device;

applying a predetermined delay, wherein the duration of the predetermined delay is configurable; and

after said predetermined delay, starting the appropriate power transition.

22. A method as claimed in claim 21 wherein the power state transition command is received from a device processor.

23. A method as claimed in claim 21 wherein the predetermined delay applied has a duration based on a delay setting.

28. A power management integrated circuit being operable, in use, to provide a plurality of power states, wherein the power management integrated circuit is configured to transition from a present power state to another power state in response to a power state transition command, and wherein the power management integrated circuit is arranged to provide a predetermined delay between receipt of a power state transition command and start of the appropriate power state transition, wherein the power management integrated circuit is configured to receive at least some power state transition commands from an operating system of a host device and to apply said predetermined delay in response to a power state transition command received from said operating system, wherein the power management integrated circuit is arranged, on receipt of a power transition command, to send a power transition indication signal to at least one output, wherein the power transition indication signal is an interrupt signal for a device processor.

29. A power management integrated circuit being operable, in use, to provide a plurality of power states, wherein the power management integrated circuit is configured to transition from a present power state to another power state in response to a power state transition command, and wherein the power management integrated circuit is arranged to provide a predetermined delay between receipt of a power state transition command and start of the appropriate power state transition, wherein the power management integrated circuit is configured to receive at least some power state transition commands from an operating system of a host device and to apply said predetermined delay in response to a power state transition command received from said operating system, and wherein the power management integrated circuit is adapted to, on power up of the power management integrated circuit, to set the duration of the predetermined delay based on a setting in a non-volatile memory.