Deep idle mode

• US 8,612,786 B1
• Filed: 09/24/2010
• Issued: 12/17/2013
• Est. Priority Date: 09/24/2010
• Status: Expired due to Fees

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Lachwani, Manish, Berbessou, David
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US12/890,003
• Time in Patent Office: 1,180 Days
• Field of Search: 713/300, 713/320, 713/322, 713/323, 713/324, 713/600, 713/601
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During deep idle mode, a root clock such as the microcontroller unit phase-locked loop (MPLL) is scaled or gated entirely and other clocks such as the processor, memory, and general purpose timer clocks may be scaled. To maintain functionality while these clocks are scaled or gated, an external clock source couples to the processor, memory, and a general purpose timer.

Claims

1. An electronic device comprising:

a processor;

memory coupled to the processor;

a root clock coupled to the processor and configured to provide a first timing signal to the processor and the memory;

an external clock coupled to the processor, the memory, or both; and

a deep idle mode module, stored in the memory and configured to execute on the processor to;

determine that the electronic device is idle;

at least partly in response to determining that the electronic device is idle;

scale down the root clock from a first frequency to a second frequency, wherein the second frequency is greater than zero;

in response to determining that the root clock has been scaled down to the second frequency that is greater than zero, switch at least one of the processor or the memory from the root clock to receive a second timing signal from the external clock; and

after the switching from the root clock, gate the root clock.

2. The electronic device of claim 1, wherein the root clock comprises a microcontroller unit phase-locked loop (MPLL) clock.

3. The electronic device of claim 1, further comprising a general purpose timer (GPT), wherein the deep idle mode module is further configured to execute on the processor to switch the GPT to the external clock to receive the second timing signal at least partly in response to determining that the electronic device is idle.

4. The electronic device of claim 1, wherein the external clock comprises a low frequency clock having a frequency of less than one (1) MHz.

5. The electronic device of claim 1, further comprising a memory clock, and wherein the deep idle mode module is further executable on the processor to scale the memory clock from a first memory clock frequency to a second memory clock frequency prior to the gating of the root clock.

6. The electronic device of claim 1, further comprising a general purpose timer (GPT) having a clock source, wherein the deep idle mode module is further configured to execute on the processor to:

switch the clock source of the GPT to the external clock at least partly in response to determining that the root clock has been scaled down to the second frequency that is greater than zero; and

recalibrate a timer frequency of the GPT at least in part due to switching of the clock source of the GPT to the external clock.

7. The electronic device of claim 1, wherein the determining that the electronic device is idle comprises:

determining a number of timer interrupts received by the processor in a specified period; and

when the number of timer interrupts received by the processor in the specified period is below a pre-determined threshold, designating the electronic device as idle.

8. The electronic device of claim 1, wherein the determining that the electronic device is idle comprises:

setting a sample period;

counting a number of consecutive sample periods during which a specified clock of the electronic device is at or below a specified clock rate; and

when the number of consecutive sample periods exceeds a pre-determined threshold, determining that the electronic device is idle.

9. The electronic device of claim 1, wherein the deep idle mode module is further configured to execute on the processor to:

after the gating of the root clock, receive a wake-up event on the processor;

disable interrupts on the processor;

enable the root clock;

propagate a clock value corresponding to a frequency of the root clock down a clock tree of the electronic device; and

enable the interrupts on the processor.

10. The electronic device of claim 1, wherein the deep idle mode module is further configured to execute on the processor to:

prior to the gating of the root clock, propagate a clock value associated with the second frequency of the root clock that is greater than zero along a clock tree of the electronic device, wherein the clock tree comprises the root clock and at least one of;

a processor clock of the electronic device;

a memory clock of the electronic device;

or

a general purpose timer of the electronic device

wherein the root clock is gated in response to determining that the clock value associated with the second frequency of the root clock that is greater than zero has been propagated along the clock tree of the electronic device.

11. An electronic device comprising:

a processor;

memory coupled to the processor;

a root clock to provide a first timing signal to at least the memory;

a memory clock;

an external clock; and

a module maintained in the memory which, when executed by the processor, causes the processor to perform operations including;

in response to determining that the root clock has been scaled down from a first frequency to a second frequency that is greater than zero, switching at least the memory from receiving the first timing signal from the root clock to receiving a second timing signal from the external clock;

scaling down the memory clock from a first memory clock frequency to a second memory clock frequency; and

after the scaling down of the memory clock, gating the root clock.

12. The electronic device of claim 11, the operations further comprising:

determining a number of timer interrupts received by the processor in a specified period; and

in response to determining that the number of timer interrupts received by the processor in the specified period is below a pre-determined threshold, performing the scaling down of the root clock, the switching from the root clock, the scaling down of the memory clock, and the gating of the root clock.

13. The electronic device of claim 11, the operations further comprising:

setting a sample period;

counting a number of consecutive sample periods during which a specified clock of the electronic device is at or below a specified clock rate; and

in response to determining that the number of consecutive sample periods exceeds a pre-determined threshold, performing the scaling down of the root clock, the switching from the root clock, the scaling down of the memory clock, and the gating of the root clock.

14. The electronic device of claim 11, further comprising a general purpose timer (GPT), the operations further comprising:

prior to the scaling down of the memory clock, switching the GPT to the external clock to receive the second timing signal from the external clock; and

recalibrating a timer frequency of the GPT at least in part due to the switching of the GPT to receive the second timing signal from the external clock.

15. A method comprising:

under control of a processor of an electronic device specifically configured with executable instructions,

sending a first timing signal from a root clock to at least one of the processor or a memory;

determining that the electronic device is idle;

at least partly in response to the determining that the electronic device is idle;

disabling interrupts received within the electronic device;

after the disabling of the interrupts, scaling down the root clock from a first frequency to a second frequency, wherein the second frequency is greater than zero;

in response to determining that the root clock has been scaled down to the second frequency that is greater than zero, switching the processor, the memory, or both from receiving the first timing signal from the root clock to receiving a second timing signal from an external clock; and

gating the root clock.

16. The method of claim 15, further comprising, prior to the gating of the root clock:

gating core clocks of the electronic device or confirming that the core clocks are gated; and

propagating a value associated with the second frequency of the root clock that is greater than zero down a clock tree of the electronic device,

wherein the root clock is gated in response to determining that the value associated with the second frequency of the root clock that is greater than zero has been propagated down the clock tree of the electronic device.

17. The method of claim 15, further comprising:

enabling the external clock of the electronic device;

switching a general purpose timer (GPT) to the external clock;

recalibrating a timer frequency of the GPT;

scaling a memory clock of the electronic device;

disabling processor clock scaling;

performing the switching of the processor to the external clock;

performing the switching of the memory to the external clock;

propagating clock values associated with the second timing signal of the external clock throughout a clock tree of the electronic device;

enabling the interrupts received within the electronic device after the gating of the root clock; and

enabling the processor clock scaling after the enabling of the interrupts.

18. The method of claim 15, further comprising, after the gating of the root clock:

receiving a wake-up event on the processor;

disabling interrupts on the processor;

enabling the root clock;

propagating a clock value corresponding to a frequency of the root clock down a clock tree of the electronic device; and

enabling the interrupts on the processor.

19. The method of claim 15, further comprising:

enabling the interrupts received within the electronic device after the gating of the root clock; and

after the enabling of the interrupts, scaling down a processor clock of the electronic device.

20. One or more computer-readable storage media storing instructions that, when executed by a processor of an electronic device, cause the processor to perform operations comprising:

determining that the electronic device is idle; and

at least partly in response to the determining that the electronic device is idle;

scaling down a root clock from a first frequency to a second frequency, wherein the second frequency is greater than zero; and

in response to determining that the root clock has been scaled down to the second frequency that is greater than zero, switching at least one of the processor or the memory from receiving a first timing signal from the root clock to receiving a second timing signal from an external clock.

21. The one or more computer-readable storage media of claim 20, the operations further comprising gating the root clock after the switching from the root clock.

22. The one or more computer-readable storage media of claim 20, the operations further comprising:

propagating a value associated with the second frequency of the root clock that is greater than zero down a clock tree of the electronic device, wherein the clock tree comprises the root clock and at least one of;

a processor clock of the electronic device;

a memory clock of the electronic device;

or

a general purpose timer of the electronic device; and

gating the root clock in response to determining that the value associated with the second frequency of the root clock that is greater than zero has been propagated down the clock tree of the electronic device.

23. The one or more computer-readable storage media of claim 20, wherein:

the electronic device includes an electronic book reader device; and

the electronic book reader device is determined to be idle at least in part based on a system event that is generated in response to detecting that a user has turned a page of an electronic book.