Apparatus and methods for interleaving in a forward link only system
First Claim
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1. A method of transmitting a plurality of codeblocks in a communication system, the method comprising:
- turbo encoding a plurality of codeblocks using a plurality of long turbo encoders to generate a plurality of turbo encoded codeblocks;
interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme;
transmitting the plurality of turbo encoded and M-sequence bit interleaved codeblocks;
wherein the M-sequence bit interleaving scheme comprises;
pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register;
utilizing the linear feedback shift register internal state as a memory location address in a buffer;
obtaining a bit of at least one of the plurality of turbo encoded codeblocks stored in an input buffer at the M-sequence state memory address; and
storing the obtained bit in a next available memory location address in an output buffer.
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Abstract
Methods and devices for encoding and interleaving data packets for broadcast and for de-interleaving and decoding data packets in a communication system eliminate detrimental biasing effects by using pseudo-random M-sequence bit encoding as part of the turbo encoding and decoding. The use of pseudo-random M-sequence bit encoding mitigates biasing effects that may otherwise be introduced if conventional r-c interleaving is applied to long turbo encoded data which would degrade reception in the presence of broadcast interference.
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Citations
29 Claims
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1. A method of transmitting a plurality of codeblocks in a communication system, the method comprising:
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turbo encoding a plurality of codeblocks using a plurality of long turbo encoders to generate a plurality of turbo encoded codeblocks; interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme; transmitting the plurality of turbo encoded and M-sequence bit interleaved codeblocks; wherein the M-sequence bit interleaving scheme comprises; pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register; utilizing the linear feedback shift register internal state as a memory location address in a buffer; obtaining a bit of at least one of the plurality of turbo encoded codeblocks stored in an input buffer at the M-sequence state memory address; and storing the obtained bit in a next available memory location address in an output buffer. - View Dependent Claims (2, 3, 4)
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5. An apparatus for use in a broadcast communication system, comprising:
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means for turbo encoding a plurality of codeblocks using a plurality of long turbo encoders to generate a plurality of turbo encoded codeblocks; means for interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme; and means for transmitting the plurality of turbo encoded and M-sequence bit interleaved codeblocks; wherein the means for interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme comprises; means for pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register; means for utilizing the linear feedback shift register internal state as a memory location address in a buffer; and means for storing a next available bit of at least one of the plurality of turbo encoded codeblocks to the memory location address in the buffer. - View Dependent Claims (6, 7, 8)
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9. An apparatus for use in a broadcast communication system, comprising:
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a memory buffer; a processor coupled to the memory buffer, wherein the processor is configured with software instructions to perform steps comprising; turbo encoding a plurality of codeblocks using a plurality of long turbo encoders to generate a plurality of turbo encoded codeblocks; interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme; transmitting the plurality of turbo encoded and M-sequence bit interleaved codeblocks; pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register; utilizing the linear feedback shift register internal state as a memory location address in the memory buffer; and storing a next available bit of at least one of the plurality of turbo encoded codeblocks to the memory location address in the buffer. - View Dependent Claims (10, 11, 12)
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13. A non-transitory storage medium having stored thereon processor-executable software instructions configured to cause a processor in a broadcast communication system to perform steps comprising:
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turbo encoding a plurality of codeblocks using a plurality of long turbo encoders to generate a plurality of turbo encoded codeblocks; interleaving each of the plurality of turbo encoded codeblocks using an M-sequence bit interleaving scheme; transmitting the plurality of turbo encoded and M-sequence bit interleaved codeblocks; pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register; utilizing the linear feedback shift register internal state as a memory location address in the memory buffer; and storing a next available bit of at least one of the plurality of turbo encoded codeblocks to the memory location address in the buffer. - View Dependent Claims (14, 15, 16)
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17. An apparatus for use in a broadcast communication system, comprising:
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a plurality of long turbo encoders each configured to encode one of a plurality of codeblocks for transmission in a channel thereby generating a plurality of turbo encoded codeblocks; at least one M-sequence interleaver configured to interleave each of the plurality of turbo encoded codeblocks; a transmitter for transmitting the plurality of turbo encoded and m-sequence bit interleaved codeblocks; an M-sequence pseudo-random sequence generator; a maximum length linear feedback shift register for generating the M-sequence pseudo-random sequence; a memory buffer; a processor configured to interpret each member of the M-sequence pseudo-random sequence as a memory location address in the memory buffer and to store a next available bit of at least one of the plurality of turbo encoded codeblocks to the memory location address in the memory buffer. - View Dependent Claims (18, 19, 20, 21)
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22. A method of decoding and de-interleaving a received data signal in a receiver device, the method comprising:
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receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using a round-robin de-interleaver to generate a plurality of turbo encoded codeblocks; storing each of the plurality of turbo encoded codeblocks in a corresponding codeblock input buffer; pseudo-randomly generating an M-sequence state in a maximum length linear feedback shift register; using the M-sequence state as a memory location address in the codeblock input buffer; and storing a next available soft bit stored in the codeblock input buffer in a codeblock output buffer at a location corresponding the M-sequence bit memory location address.
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23. A method of decoding and de-interleaving a received data signal in a communication system, the method comprising:
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receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using an M-sequence de-interleaver to generate a plurality of turbo encoded codeblocks; and decoding each of the plurality of codeblocks using a corresponding plurality of long turbo decoders; wherein de-interleaving the received data signal using the M-sequence bit de-interleaver comprises; storing received data signal in an input buffer; pseudo-randomly generating an M-sequence bit in a maximum length linear feedback shift register; utilizing the M-sequence bit as a memory location address in the input buffer; and storing a next available soft bit in the input buffer at a location in an output buffer corresponding to the M-sequence memory location address.
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24. An apparatus for use in a communication receiver device, comprising:
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means for receiving a long turbo encoded and M-sequence interleaved data signal; means for de-interleaving the received data signal using a round-robin de-interleaver to generate a plurality of turbo encoded codeblocks; means for storing each of the plurality of turbo encoded codeblocks in a corresponding codeblock input buffer; means for pseudo-randomly generating an M-sequence state in a maximum length linear feedback shift register; means for using the M-sequence state as a memory location address in a codeblock input buffer; and means for storing a next available a soft bit stored in the codeblock input buffer in a codeblock output buffer at a location corresponding to the M-sequence memory location address.
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25. An apparatus for use in a communication receiver device, comprising:
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means for receiving a long turbo encoded and M-sequence interleaved data signal; means for de-interleaving the received data signal using an M-sequence de-interleaver to generate a plurality of turbo encoded codeblocks; and means for decoding each of the plurality of codeblocks using a corresponding plurality of long turbo decoders; wherein the means for de-interleaving the received data signal using the M-sequence bit de-interleaver comprises; means for storing received data signal in an input buffer; means for reverse pseudo-randomly generating an M-sequence bit in a maximum length linear feedback shift register; means for utilizing the M-sequence bit as a memory location address in the input buffer; means for storing a next available soft the bit in the input buffer at a location in an output buffer corresponding to the M-sequence memory location address.
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26. An apparatus for use in a communication receiver device, comprising:
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a memory; and a processor coupled to the memory, wherein the processor is configured with software instructions to perform steps comprising; receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using a round-robin de-interleaver scheme to generate a plurality of turbo encoded codeblocks; storing each of the plurality of turbo encoded codeblocks in a corresponding codeblock input buffer; reverse pseudo-randomly generating an M-sequence state in a maximum length linear feedback shift register; using the M-sequence state as a memory location address in the corresponding codeblock input buffer; and storing a next available soft bit stored in the corresponding codeblock input buffer in a codeblock output buffer at a location corresponding to the M-sequence memory location address.
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27. An apparatus for use in a communication receiver device, comprising:
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a memory; and a processor coupled to the memory, wherein the processor is configured with software instructions to perform steps comprising; receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using an M-sequence de-interleaver scheme to generate a plurality of turbo encoded codeblocks; long turbo decoding each of the plurality of codeblocks; storing the received data signal in an input buffer; reverse pseudo-randomly generating an M-sequence bit in a maximum length linear feedback shift register; utilizing the M-sequence bit as a memory location address in the input buffer; and storing a next available soft bit in the input buffer at a location in an output buffer corresponding to the M-sequence memory location address.
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28. A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a mobile device processor to perform steps comprising:
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receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using a round-robin de-interleaver scheme to generate a plurality of turbo encoded codeblocks; storing each of the plurality of turbo encoded codeblocks in a corresponding codeblock input buffer; pseudo-randomly generating a maximum length M-sequence state in a linear feedback shift register; using the M-sequence state as a memory location address in the codeblock input buffer; and storing a next available soft bit stored in the codeblock input buffer in a codeblock output buffer at a location corresponding to the M-sequence memory location address.
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29. A non-transitory processor-readable storage medium having stored thereon processor-executable software instructions configured to cause a receiver device processor to perform steps comprising:
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receiving a long turbo encoded and M-sequence interleaved data signal; de-interleaving the received data signal using an M-sequence de-interleaver scheme to generate a plurality of turbo encoded codeblocks; long turbo decoding each of the plurality of codeblocks; storing the received data signal in an input buffer; reverse pseudo-randomly generating an M-sequence bit in a maximum length linear feedback shift register; utilizing the M-sequence bit as a memory location address in the input buffer; and storing a next available soft bit in the input buffer at a location in an output buffer corresponding the M-sequence bit memory location address.
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Specification