CMOS structures and processes based on selective thinning

• US 8,614,128 B1
• Filed: 08/22/2012
• Issued: 12/24/2013
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Thompson, Scott E., Scudder, Lance, Zhao, Dalong, Ranade, Pushkar, Gregory, Paul E., Hoffmann, Thomas, Sridharan, U. C., Duane, Michael
• Primary Examiner(s): Coleman, William D
• Assistant Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US13/591,767
• Time in Patent Office: 489 Days
• Field of Search: 438/13, 438/275, 257/E21.63
• US Class Current: 438/275
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

Claims

1. A method of fabricating semiconductor devices, comprising:

providing a substrate having a semiconducting surface and a first layer disposed directly on the semiconducting surface, the semiconducting surface having formed therein a plurality of active regions, the plurality of active regions comprising at least a first active region and a second active region, each of the first active region and the second active region comprising the first layer and a second layer, the first layer comprising a substantially undoped layer that extends across the semiconducting surface and the second layer comprising at least one highly doped screening layer, a combination of the first layer and the second layer defining at least one device characteristic for the semiconductor devices in each of the first active region and the second active region;

identifying at least one device characteristic target required for the semiconductor devices in at least a portion of the first active region, the at least one device characteristic target comprising at least a threshold voltage target;

tuning the at least one device characteristic in the portion of the first active region to match the at least one device characteristic target by performing a first process with the substrate to remove a part of the first layer to reduce a thickness of the first layer in the portion of the first active region without a corresponding thickness reduction of the first layer in the second active region, the portion of the first active region defining at least one processed region; and

forming the semiconductor devices in at least the one processed region and the second active region,

wherein a gate for the semiconductor devices is formed directly on the first layer, and wherein the part of the first layer is selected based on the at least one device characteristic target.

2. The method of claim 1, wherein the first process comprises:

forming at least one masking layer on the substrate, the at least one masking layer comprising a pattern having at least one opening for defining the at least one processed region; and

applying a material removal process to the substrate, wherein the material removal process preferentially removes a portion of the material comprising the first layer over the at least one masking layer,

wherein the material removal process comprises a self-limiting process.

3. The method of claim 1, wherein the at least one device characteristic target further comprises at least one of a leakage current target, a subthreshold swing target, and a drain-induced barrier lowering target.

4. The method of claim 1, wherein the first process comprises:

forming at least one masking layer on the substrate, the at least one masking layer comprising a pattern having at least one opening for defining the at least one processed region;

applying a transformation process to the substrate, wherein the transformation process alters a composition of the part of the first layer in the at least one processed region to yield transformed material; and

applying a material removal process to the substrate, wherein the material removal process preferentially removes the transformed material over other materials.

5. The method of claim 4, wherein the transformation process comprises at least one of an oxidation process or an amorphization process.

6. The method of claim 1, further comprising:

prior to the step of forming, performing the steps of

identifying an additional threshold voltage adjustment required for the semiconductor devices in at least a selected portion of the at least one processed region based on a configuration of the at least one processed region;

performing a second process with the substrate to remove an additional part of the first layer to reduce a thickness of the substantially undoped layer for at least a selected portion of the at least one processed region without a corresponding thickness reduction of the thickness in the first layer for the second active region or the thickness of the first layer for other portions of the at least one processed region,

wherein the additional part of the first layer is selected based at least on the additional threshold voltage adjustment.

7. The method of claim 1, wherein the method further comprises:

forming trench regions separating the plurality of active regions, the trench regions being filled with an electrical insulator material; and

if the performing of the first process precedes the forming of the trench regions, performing a second process with the substrate to remove a portion of the electrical insulator material associated with the at least one processed regions so that a step height associated with the trench regions and the semiconducting surface is substantially the same across the substrate.

8. A method of fabricating an integrated circuit comprising a plurality of semiconductor devices defined in a plurality of active regions of a substrate having a semiconducting surface and a first layer disposed directly on the semiconducting surface, the plurality of active regions comprising at least a first active region and a second active region, each of the first active region and the second active region comprising the first layer and a second layer, the first layer comprising a substantially undoped layer of a pre-defined thickness range layer that extends across the semiconducting surface and the second layer comprising a highly doped screening layer, the method comprising:

identifying a first target thickness range for the substantially undoped layer in the first active region based on at least one pre-defined device characteristic target for the first active region and pre-defined doping conditions for the substrate, the at least one pre-defined device characteristic target comprising a threshold voltage target;

if the first target thickness range and the pre-defined thickness range fail to meet a minimum overlap criteria, tuning a threshold voltage for the first active region by determining a first amount of the first layer to remove from the first active region to provide a first reduced thickness range for the substantially undoped layer in the first active region that meets the minimum overlap criteria;

performing a first process with the substrate to remove the first amount of the first layer from the selected portion without removing the first amount in other portions of the semiconducting surface; and

forming semiconductor devices in at least the selected portion and the second active region, wherein a gate for the semiconductor devices is formed directly on the first layer.

9. The method of claim 8, further comprising providing a physical design for the plurality of active regions;

and wherein the determining further comprises;

identifying portions of the physical design associated with the first active region, and

inserting design blocks into the physical design defining a masking layer removing the first amount from the first active regions.

10. The method of claim 8, further comprising:

identifying a second target thickness range for the substantially undoped layer in a a selected portion of the first active region based on the at least one pre-device device characteristic target for the selected portion and the pre-defined doping conditions; and

if the second target thickness range and the first target thickness range fail to meet a minimum overlap criteria, tuning a threshold voltage for the selected portion by determining a second amount of the first layer to remove from the selected portion in order to provide a reduced thickness range for the substantially undoped layer in the selected portion that meets the minimum overlap criteria.

11. The method of claim 8, further comprising:

if the first amount is greater than a thickness reduction criteria, identifying a combination of at least one adjustment of the pre-defined doping conditions and a second amount of the first layer to remove from the selected portion less than the first amount that results in the plurality of devices meeting the pre-defined device characteristic targets and the second amount meeting the thickness reduction criteria.

12. The method of claim 8, the determining of the first amount further comprising,

if the pre-defined doping conditions for the plurality of devices associated with the at first active region specify conditions for at least one implant defining the highly doped screening layer and at least one other implant, selecting the first amount in combination with adjustments for the pre-defined doping conditions that reduce or eliminate the at least one other implant.

13. A method of fabricating an integrated circuit, comprising:

providing a substrate with a semiconducting surface, the semiconducting surface comprising silicon;

defining a plurality of active regions in the semiconducting surface, the plurality of active regions comprising at least one first active region with a first highly doped screening layer and at least one second active region with a second highly doped screening layer;

forming a substantially undoped epitaxial layer comprising silicon that extends across the semiconducting surface, a combination of the substantially undoped epitaxial layer and the first highly doped screening layer defining a threshold voltage for semiconductor devices in the at least one first active region, and a combination of the substantially undoped epitaxial layer and the second highly doped screening layer defining the threshold voltage for semiconductor devices in the at least one second active region;

after said forming, identifying an threshold voltage adjustment required for the semiconductor devices in the at least one first active region;

tuning the threshold voltage for the at least one first active region by performing a first process with the substrate that removes a portion of the substantially undoped epitaxial layer over the at least one first active region without removing a corresponding portion of the layer of the substantially undoped epitaxial layer over the at least one second active region;

forming semiconductor devices in plurality of active regions, wherein a gate for the semiconductor devices is disposed directly on the substantially undoped epitaxial layer, and

wherein the portion of the first layer is selected based at least on the threshold voltage adjustment.

14. The method of claim 13, wherein the first process comprises:

forming at least one masking layer on the substantially undoped epitaxial layer, the at least one masking layer comprising a pattern having at least one opening corresponding to the at least one first active region; and

applying a material removal process to the substrate, wherein the material removal process preferentially removes the substantially undoped epitaxial layer over the at least one masking layer.

15. The method of claim 14, wherein the material removal process comprises at least one of a wet silicon etch process, a dry silicon etch process, or a plasma assisted silicon etch process.

16. The method of claim 13, wherein the first process comprises:

forming at least one masking layer on the substantially undoped epitaxial layer, the at least one masking layer comprising a pattern having at least one opening corresponding to the at least one first active region;

applying an oxidation process the substrate, the oxidation process selected to consume the portion of the substantially undoped epitaxial layer to form a silicon oxide layer; and

applying a material removal process to the substrate, wherein the material removal process removes the silicon oxide layer without completely removing the at least one masking layer.

17. The method of claim 16, wherein the oxidation process is self-limiting.

18. The method of claim 13, wherein the at least one first active region comprises a plurality of first active regions, and further comprising:

performing a second process with the substrate that preferentially removes a portion of the substantially undoped epitaxial layer over the at least one second active region without substantially affecting the substantially undoped epitaxial layer over the plurality of first active regions.