Thin film transistor and method of forming the same

• US 8,614,442 B2
• Filed: 02/17/2011
• Issued: 12/24/2013
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-chul, Park, Young-soo, Kim, Sun-Il
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US12/929,818
• Publication Number:
  US 20110141100A1
• Time in Patent Office: 1,041 Days
• Field of Search: 257/43, 257/E21.467, 257/E29.094, 438/104, 345/214
• US Class Current: 257/43
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.

Claims

1. A thin film transistor, comprising:

a channel layer including an oxide semiconductor material;

a source electrode and a drain electrode facing each other on the channel layer;

a protective layer under the source electrode and the drain electrode and covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface;

a gate electrode configured to apply an electric field to the channel layer; and

a gate insulating layer interposed between the gate electrode and the channel layer.

wherein the protective layer having the dumbbell shape includes a central portion and enlarged portions disposed at both ends of the central portion, and a width of the enlarged portions is greater than a width of the channel layer, so that the entire region of the channel layer except for the two regions of the upper surface is covered by the protective layer.

2. The thin film transistor of claim 1, wherein the channel layer is a ZnO based material layer.

3. The thin film transistor of claim 2, wherein the channel layer is a a(In₂O₃).b(Ga₂O₃).c(ZnO) layer, where a, b, and c are real numbers such that a≧

0, b≧

0, and c>

0.

4. The thin film transistor of claim 3, wherein the channel layer is a a(In₂O₃).b(Ga₂O₃).c(ZnO) layer, where a, b, and c are real numbers such that a≧

1, b≧

1, and 0<

c≦

1.

5. The thin film transistor of claim 1, wherein

the two regions of the channel layer are provided as contact regions, and

the source and drain electrodes contact the channel layer at the contact regions.

6. The thin film transistor of claim 1, wherein when the protective layer has the dumbbell shape, the protective layer covers a region of the upper surface of the channel layer except for central regions of both ends of the upper surface.

7. The thin film transistor of claim 1, wherein when the protective layer has the rectangular shape, the protective layer covers a region of the upper surface of the channel layer except for both ends of the upper surface.

8. The thin film transistor of claim 1, wherein the protective layer is at least one selected from a group including a silicon oxide layer and a silicon nitride layer.

9. The thin film transistor of claim 1, further comprising:

ohmic contact layers between the channel layer and the source electrode and between the channel layer and the drain electrode.

10. The thin film transistor of claim 9, wherein the ohmic contact layers comprise a conductive oxide having an oxygen content that is less than an oxygen content of the channel layer.

11. The thin film transistor of claim 1, wherein the gate electrode is above the channel layer.

12. The thin film transistor of claim 1, wherein the gate electrode is below the channel layer.

13. A flat panel display comprising the transistor of claim 1.

14. A method of manufacturing a thin film transistor comprising:

forming a channel layer including an oxide semiconductor material and a protective layer covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface;

forming a source electrode and a drain electrode facing each other and contacting the two regions of the channel layer;

forming a gate insulating layer covering the protective layer, the source electrode, and the drain electrode; and

forming a gate electrode on the gate insulating layer above the channel layer.

15. The method of claim 14, wherein the channel layer is a ZnO based material layer.

16. The method of claim 14, further comprising:

treating the surface of the channel layer using oxygen plasma after the forming of the channel layer and before the forming of the protective layer.

17. The method of claim 14, further comprising:

wet washing the surface of the channel layer using a washing solution after the forming of the channel layer and before the forming of the protective layer.

18. A method of manufacturing a thin film transistor, comprising:

forming a gate electrode;

forming a gate insulating layer covering the gate electrode;

forming a channel layer including an oxide semiconductor material on the gate insulating layer above the gate electrode and a protective layer covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface; and

forming a source electrode and a drain electrode facing each other on the channel layer and contacting the two regions of the channel layer,

wherein the protective layer is under the source electrode and the drain electrode,

the gate electrode is configured to apply an electric field to the channel layer;

the gate insulating layer interposed between the gate electrode and the channel layer, and

the protective layer having the dumbbell shape includes a central portion and enlarged portions disposed at both ends of the central portion, and a width of the enlarged portions is greater than a width of the channel layer, so that the entire region of the channel layer except for the two regions of the upper surface is covered by the protective layer.

19. The method of claim 18, wherein the channel layer is a ZnO based material layer.

20. The method of claim 18, further comprising:

treating the surface of the channel layer using oxygen plasma after the forming of the channel layer and before the forming of the protective layer.

21. The method of claim 18, further comprising:

wet washing the surface of the channel layer using a washing solution after the forming of the channel layer and before the forming of the protective layer.