Thin film transistor and method of forming the same
First Claim
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1. A thin film transistor, comprising:
- a channel layer including an oxide semiconductor material;
a source electrode and a drain electrode facing each other on the channel layer;
a protective layer under the source electrode and the drain electrode and covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface;
a gate electrode configured to apply an electric field to the channel layer; and
a gate insulating layer interposed between the gate electrode and the channel layer.wherein the protective layer having the dumbbell shape includes a central portion and enlarged portions disposed at both ends of the central portion, and a width of the enlarged portions is greater than a width of the channel layer, so that the entire region of the channel layer except for the two regions of the upper surface is covered by the protective layer.
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Abstract
A thin film transistor (TFT) may include a channel layer, a source electrode, a drain electrode, a protective layer, a gate electrode, and/or a gate insulating layer. The channel layer may include an oxide semiconductor material. The source electrode and the drain electrode may face each other on the channel layer. The protective layer may be under the source electrode and the drain electrode and/or may cover the channel layer. The gate electrode may be configured to apply an electric field to the channel layer. The gate insulating layer may be interposed between the gate electrode and the channel layer.
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Citations
21 Claims
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1. A thin film transistor, comprising:
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a channel layer including an oxide semiconductor material; a source electrode and a drain electrode facing each other on the channel layer; a protective layer under the source electrode and the drain electrode and covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface; a gate electrode configured to apply an electric field to the channel layer; and a gate insulating layer interposed between the gate electrode and the channel layer. wherein the protective layer having the dumbbell shape includes a central portion and enlarged portions disposed at both ends of the central portion, and a width of the enlarged portions is greater than a width of the channel layer, so that the entire region of the channel layer except for the two regions of the upper surface is covered by the protective layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of manufacturing a thin film transistor comprising:
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forming a channel layer including an oxide semiconductor material and a protective layer covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface; forming a source electrode and a drain electrode facing each other and contacting the two regions of the channel layer; forming a gate insulating layer covering the protective layer, the source electrode, and the drain electrode; and forming a gate electrode on the gate insulating layer above the channel layer. - View Dependent Claims (15, 16, 17)
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18. A method of manufacturing a thin film transistor, comprising:
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forming a gate electrode; forming a gate insulating layer covering the gate electrode; forming a channel layer including an oxide semiconductor material on the gate insulating layer above the gate electrode and a protective layer covering the channel layer, wherein the protective layer has a dumbbell shape or a rectangular shape covering a region of an upper surface of the channel layer except for two regions of the upper surface; and forming a source electrode and a drain electrode facing each other on the channel layer and contacting the two regions of the channel layer, wherein the protective layer is under the source electrode and the drain electrode, the gate electrode is configured to apply an electric field to the channel layer; the gate insulating layer interposed between the gate electrode and the channel layer, and the protective layer having the dumbbell shape includes a central portion and enlarged portions disposed at both ends of the central portion, and a width of the enlarged portions is greater than a width of the channel layer, so that the entire region of the channel layer except for the two regions of the upper surface is covered by the protective layer. - View Dependent Claims (19, 20, 21)
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Specification