Low cost ultra versatile mixed signal controller circuit

• US 8,614,595 B2
• Filed: 11/16/2009
• Issued: 12/24/2013
• Est. Priority Date: 11/14/2008
• Status: Active Grant

• Current Assignee: Beniamin Acatrinei
• Original Assignee: Beniamin Acatrinei
• Inventors: Acatrinei, Beniamin
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US12/619,548
• Publication Number:
  US 20100164579A1
• Time in Patent Office: 1,499 Days
• Field of Search: 327306-333, 327172-175, 332109-111
• US Class Current: 327/172
• CPC Class Codes: H02M 1/4208 Arrangements for improving power factor of AC input
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low-cost ultra-versatile pulse width modulation (PWM)-timer controller system is disclosed for use in the electric power management industry. Using different voltage/current buffer devices, the present system is capable of performing a variety of control applications, including for example as a pulse width modulation controller, power factor correction circuit, silicon controlled rectifier or thyristor, zero-voltage drive circuit, AC/DC boost converter, battery charger, motor RPM controller, timer or clock, light intensity controller, temperature range controller, pressure controller, sensing/monitoring/warning system, or analog logic circuit.

Claims

1. A pulse width modulation controller system, having a plurality of circuits and a plurality of terminals, for control of automation circuits, AC-DC, DC-DC and power factor correction converter circuits, the plurality of circuits comprising:

an under-voltage lock-out circuit, operatively coupled with a first terminal of the plurality of terminals of the controller system, for internally supplying power to the controller system only when an external supply voltage reaches a pre-established voltage amount and shutting down the controller system'"'"'s internal supply when the external supply voltage decreases down to an amount lower than another pre-established limit;

a voltage reference and internal bias circuit, operatively coupled to a second terminal of the plurality of terminals of the controller system, for providing precise and stable supply voltages to a first set of one or more circuits of the controller system;

a driver circuit, operatively coupled to at least a third terminal of the plurality of terminals of the controller system, for generating square wave pulses for driving external transistors;

an oscillator circuit, operatively coupled to a fourth terminal of the plurality of terminals of the controller system, for generating a voltage ramp signal allowing voltage mode of operations and a fast slew rate rectangular SET pulse for validating the start timing of each pulse outputted by the driver circuit;

a voltage ramp buffer circuit, operatively coupled between an output of the oscillator circuit and a fifth terminal of the plurality of terminals of the controller system, for mixing the voltage ramp signal with a current feedback signal inputted at the fifth terminal of the plurality of terminals of the controller system, and for allowing a combination of voltage mode and current mode pulse width modulation control operations, having synchronization inputs and/or outputs;

a current spike filter circuit, operatively coupled between the fifth terminal and one or more circuits of the plurality of circuits of the controller system, for eliminating current spikes included in current feedback signals, having synchronization inputs and outputs;

an error amplifier circuit, operatively coupled between sixth and seventh terminals of the plurality of terminals of the controller circuit, the sixth terminal being an input terminal and the seventh terminal being an output terminal, for sensing voltage signals having an amplitude higher than a pre-established limit;

a voltage limiter circuit, operatively coupled at least with an output from the error amplifier circuit, for limiting an output voltage from the error amplifier circuit down to a pre-established limit;

a soft start circuit operatively coupled between the sixth and seventh terminals of the error amplifier circuit and to one or more circuits of the plurality of circuits of the controller system, for forcing the driver circuit output signal'"'"'s duty cycle to increase smoothly at any time when the controller system is connected to a supply source, having synchronization inputs and/or outputs;

a PWM comparator circuit, operatively coupled with the error amplifier circuit via an output of the current spike filter circuit, for comparing the voltage ramp signal with the signal outputted by the error amplifier circuit and for outputting a fast slew rate rectangular RESET pulse and for shutting down the controller system'"'"'s driver circuit output driving pulse at any time when the voltage amount outputted by the current spike filter circuit is larger than the amount of voltage outputted by the voltage limiter circuit, having synchronization inputs and/or outputs;

a PWM logic circuit, operatively coupled with the oscillator and PWM comparator circuits, for processing the SET and RESET pulse signals and for prohibiting more than one output pulse of the driver circuit per one oscillator cycle, having synchronization inputs and outputs; and

a sync master switch system, operatively connected to circuits of the plurality of circuits of the controller system, having synchronization inputs and/or outputs for avoiding skipping pulses introduced when a slow slew rate voltage ramp and/or voltage mode of operations are used, and for enabling control of the output driving pulses signal from over 99% down to less than 1% duty cycle by minimizing a signal delay introduced by one or more of the plurality of circuits processing operations, and by synchronizing the SET and RESET pulses either by delaying the SET pulse outputted by the oscillator circuit or by accelerating the decay of the RESET pulse outputted by the PWM comparator circuit, in such a manner for the RESET pulse to always reach its LOW logic state before the SET pulse reaches its HIGH logic state.

2. A system as in claim 1, wherein the oscillator circuit comprises:

a set comparator for providing a set pulse to the PWM logic circuit and for activating a discharge transistor;

a first voltage reference source for the set comparator to deliver the set pulse by comparing an inputted signal with a the first voltage reference;

a reset comparator for ending the set pulse delivered to the PWM logic circuit;

a second voltage reference source for the reset comparator to end the set pulse by comparing an inputted signal with the second voltage reference;

a synchronization comparator providing a synchronization pulse to other circuits of the controller system;

a third voltage reference source for the set comparator to deliver the synchronization pulse by comparing an inputted signal with the third voltage reference;

a set-reset latch for processing the set and reset signals;

a discharging transistor for discharging a capacitor external to the controller system and to create a voltage ramp signal;

a constant current sink for increasing the external capacitor'"'"'s discharge time precision;

a first synchronization output for pre-setting specific maximum duty cycle ratios; and

a second synchronization output for compensating signals delays that occurs between the controller system'"'"'s sub circuits.

3. A system as in claim 1, wherein the voltage ramp buffer circuit comprises:

a gated operational amplifier for buffering the voltage ramp signal;

a diode for the operational amplifier to act as a high gain high precision pull-up transistor;

an input gate for synchronizing the voltage ramp buffer with an external signal and shut-off fast its output voltage, when necessarily.

4. A system as in claim 1, wherein the voltage ramp buffer circuit comprises:

a gated operational amplifier for buffering the voltage ramp signal;

a transistor for the operational amplifier to act as a high-gain high-precision pull-up transistor; and

a gate input for synchronizing the voltage ramp buffer with an external signal and for quickly shutting off its output voltage.

5. A system as in claim 1, wherein the voltage ramp buffer circuit comprises:

an operational amplifier for buffering the voltage ramp signal;

a transistor for the operational amplifier to act as a high-gain high-precision pull-up transistor;

a silicon diode for synchronizing the voltage ramp buffer with an external signal and for quickly shutting off its output voltage; and

a resistor for limiting the operational amplifier'"'"'s output current during the time when its output is shut-off.

6. A system as in claim 1, wherein the current spike filter circuit, comprises:

a gated operational amplifier for buffering the voltage ramp and current feedback signal; and

a gate input for synchronizing the voltage ramp buffer with an external signal and for quickly shutting off its output voltage to eliminate current spikes and compensate for delays that occur in the circuit.

7. A system as in claim 1, wherein the current spike filter circuit comprises:

a high-frequency switch for eliminating current signal spikes and for compensating delays that occur in the circuit; and

a resistor for limiting the circuit current during the time the high frequency switch is ON.

8. A system as in claim 1, wherein the soft start circuit comprises:

an operational amplifier buffer having an input coupled through a silicon diode to a first voltage reference that is also coupled through a very large value first resistor and a capacitor to ground, the operational amplifier also having an output coupled to a gate of a double-emitter PNP transistor, with one emitter coupled to a direct output and the other emitter coupled through a second resistor to a resistive output.

9. A system as in claim 1, wherein the soft start circuit comprises:

a digital-to-analog converter powered by a first voltage reference and having an input coupled to either of a capacitive input or a high-frequency two-terminals clock, the digital-to-analog converter also having an output coupled to a gate of a double-emitter PNP transistor, with one emitter coupled to a direct output and the other emitter coupled through a resistor to a resistive output.

10. A system as in claim 1, wherein the PWM Comparator circuit comprises an open-loop gated amplifier and a gate input for signals synchronization.

11. A system as in claim 1, wherein the PWM Comparator circuit comprises a comparator with a reference input and a resistive signal input.

12. A system as in claim 11, wherein the PWM Comparator circuit further comprises a set-reset output latch with a set input coupled to the comparator output, an output buffer delay circuit coupled to an output of the latch and feeding back a buffered signal to a control gate of a MOSFET switch whose source/drain terminals sink the resistive signal input of the comparator to ground whenever the MOSFET switch is ON.

13. A system as in claim 1, wherein the PWM Logic circuit comprises:

a NOR gate providing output pulses to activate the driver circuit; and

a set-reset latch having an output coupled to an input of the NOR gate, coupled to receive set pulses from the oscillator circuit at a set input and to receive reset pulses from the pulse width modulation comparator at a reset input, such that the set-reset latch allows not more than one output pulse to the driver circuit per one oscillator cycle.

14. A system as in claim 13, wherein the PWM Logic circuit further comprises a synchronization circuit for synchronizing the Set and Rest pulses and a an extra latch circuit coupled from the PWM Logic circuit output to its Set input, comprising a non-inverting buffer a MOSFET transistor and a resistor for allowing fix and variable frequency mode of operations.

15. A system as in claim 13, wherein the PWM Logic circuit further comprises a synchronization circuit for synchronizing the Set and Rest pulses and a an extra latch circuit coupled from the PWM Logic circuit output to its Set input, comprising an inverting buffer and an two inputs AND gate for allowing fix and variable frequency mode of operations.

16. A system as in claim 1, wherein the master synchronization system comprises a short time delay circuit inserted into the Set signal circuit for the Rest pulse to have sufficient time to reach its Low logic level before the Set pulse reaches its Low logic level.

17. A system as in claim 1, wherein the master synchronization system circuit comprises a switching system inserted into Reset signal circuit for forcing the PWM comparator to end its outputted Reset circuit at the same time when the Voltage Ramp signal reaches its maxim voltage amount.

18. A system as in claim 1, wherein the master synchronization system circuit comprises, simultaneously, a delay circuit inserted in the Set signal circuit and a switching system inserted in the Reset signal circuit for reaching the optimal synchronization between the two signals.

19. An analog logic bistable system for controlling automation circuits, comprising:

a controller system as in claim 1 for performing the analog logic bistable function;

a first push button switch for Setting the bistable circuit;

a second push button switch for Resetting the bistable circuit; and

a bulb for displaying the bistable circuit output logic state.

20. An analog logic monostable system for controlling automation circuits, comprising:

a controller system as in claim 1 for performing the analog logic monostable function;

a first push button switch for Setting the monostable circuit; and

a bulb for displaying the monostable circuit output logic state.

21. An analog logic astable system for controlling automation circuits, comprising:

a controller system as in claim 1 for performing the analog logic astable-Clock function;

a timing circuit comprising a resistor an a capacitor for creating a Voltage Ramp signal;

a second resistor for setting the signal'"'"'s duty cycle; and

a bulb for displaying the astable circuit output logic state.

22. The system of claim 1, wherein said Fixed Frequency Voltage Mode PWM Converter Circuit is controlled by a system comprising a Under Voltage Lock-Out circuit, a Voltage Reference Circuit, a Driver Circuit, a PWM Logic Circuit, an Oscillator Circuit, a PWM Comparator Circuit, an Error Amplifier having a Compensation Circuit, a Voltage Ramp Driver Circuit in which the Oscillator signal is buffered by a Transistor or an Operational Amplifier, a Soft Start Circuit, a Current Spikes Filter Circuit, and a Synchronization System circuitry able to compensate the delay introduced by the Voltage Drive Circuit and/or the Current Spikes Filter Circuit in such a manner that the Reset pulse delivered by the PWM Comparator Circuit is in LOW state when the SET pulse delivered by the Oscillator Circuit switches to its LOW state.

23. The system of claim 1 wherein the Fixed Frequency Voltage Mode PWM Converter Circuit includes a Parallel Charge-Series Discharge Snubber Circuit comprising a Current Limiting Coil, a Snubber Capacitor and two diodes circuitry that operatively charge said Snubber Capacitor from said Full-Wave Bridge Rectifier Circuit via said Current Limiting Coil and further efficiently discharge the electrical energy accumulated in said Snubber Capacitor and said Current Limiting Coil into said Reactive Load Circuit.

24. A low-cost ultra-versatile pulse width modulation (PWM)-timer controller system to control automations, AC-DC, DC-DC and power factor correction converter circuits, the controller system including plurality of circuits and a plurality of terminals, comprising:

an under-voltage lock-out circuit operatively coupled with a first terminal of the plurality of terminals of the controller system;

a voltage gap reference circuit operatively coupled to a second terminal of the plurality of terminals of the controller system;

a driver circuit operatively coupled to at least a third terminal of the plurality of terminals of the controller system;

an oscillator circuit, operatively coupled to a fourth terminal of the plurality of terminals of the controller system, that generates a voltage ramp signal, a set signal and a synchronization signal;

a voltage ramp buffer circuit, operatively coupled between an output of the oscillator circuit and a fifth terminal of the plurality of terminals of the controller system, that allows for voltage and current mode operations having synchronization inputs and outputs;

a current spike filter circuit, operatively coupled between the fifth terminal and one or more circuits of the plurality of circuits of the controller system, having synchronization inputs and outputs;

an error amplifier circuit, operatively coupled between sixth and seventh terminals of the plurality of terminals of the controller circuit, the sixth terminal being an input terminal and the seventh terminal being an output terminal;

a voltage limiter circuit operatively coupled at least with an output from the error amplifier circuit;

a PWM comparator circuit, operatively coupled with the error amplifier circuit via an output of the current spike filter circuit, that generates a reset signal having synchronization inputs and outputs;

a PWM logic circuit, operatively coupled with the oscillator and PWM comparator circuits;

a soft start circuit that controls, simultaneously, the error amplifier sensing input and output terminals having synchronization inputs and outputs; and

a master synchronization system synchronizing all circuits that generate, buffer or receive voltage ramp, set and reset signals for the reset signal to switch, safely, to a LOW state before the set signal and the PWM logic circuit to deliver square wave pulses signals having any duty cycle ratio between 1% and 100% to the driver circuit.