Semiconductor device and method of manufacture thereof

• US 8,614,616 B2
• Filed: 01/18/2011
• Issued: 12/24/2013
• Est. Priority Date: 01/18/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Willkofer, Stefan, Wahl, Uwe, Knott, Bernhard, Hammer, Markus, Strasser, Andreas
• Primary Examiner(s): Chan, Tsz
• Application Number:
  US13/008,591
• Publication Number:
  US 20120181874A1
• Time in Patent Office: 1,071 Days
• Field of Search: 336/200, 336/232, 296/021
• US Class Current: 336/200
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19102 : in a stacked assembly with the semiconductor or solid state device
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/4902 : Electromagnet, transformer or inductor

Abstract

A semiconductor device, a method of manufacturing a semiconductor device and a method for transmitting a signal are disclosed. In accordance with an embodiment of the present invention, the semiconductor device comprises a first semiconductor chip comprising a first coil, a second semiconductor chip comprising a second coil inductively coupled to the first coil, and an isolating intermediate layer between the first semiconductor chip and the second semiconductor chip.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

manufacturing a first semiconductor chip comprising a first coil;

manufacturing a second semiconductor chip comprising a second coil, wherein bonding the first semiconductor chip with the second semiconductor chip comprises bonding the first semiconductor chip with the second semiconductor chip via an intermediate isolation film, and wherein the intermediate isolation film is a double sided adhesive film or an attach paste comprising polyimide or epoxide having a dielectric strength between 60 kV/mm to 100 kV/mm;

aligning the first semiconductor chip with the second semiconductor chip so that the first coil is arranged opposite to the second coil; and

bonding the first semiconductor chip with the second semiconductor chip.

2. The method according to claim 1, wherein the intermediate isolation film comprises a thickness of 20 μ

m to 500 μ

m.

3. The method according to claim 1, wherein aligning the first semiconductor chip with the second semiconductor chip comprises placing the first semiconductor chip face-to-face to the second semiconductor chip.

4. The method according to claim 1, further comprising thinning a substrate of the second semiconductor chip to a thickness of 60 μ

m to 300 μ

m.

5. The method according to claim 4, further comprising etching a through-via in the substrate of the second semiconductor chip.

6. The method according to claim 5, further comprising electrically connecting a connection pad of the second semiconductor chip through the through substrate via with a lead frame.

7. A method for transmitting a signal, the method comprising:

receiving a signal at a first connection pad of a first semiconductor chip;

transforming the signal from a first coil on the first semiconductor chip to a second coil on a second semiconductor chip; and

sending the signal via a second connection pad of the second semiconductor chip, wherein the first semiconductor chip and the second semiconductor chip together form a transformer, wherein the first semiconductor chip and the second semiconductor chip are attached to each other with an adhesive film or an attach paste comprising polyimide or epoxide having a dielectric strength between 60 kV/mm to 100 kV/mm.

8. The method according to claim 7, wherein the first semiconductor chip and the second semiconductor chip are galvanically separated.

9. The method according to claim 7, wherein the adhesive film or the attach paste comprises a thickness of 20 μ

m to 500 μ

m.

10. A method of manufacturing a coreless transformer, the method comprising:

forming a first coil and a first contact pad on a first side of a first semiconductor substrate;

forming a through via on a second side of the first semiconductor substrate exposing the first contact pad;

disposing an isolation film on the first side of the first semiconductor substrate;

placing the first semiconductor substrate on a second semiconductor substrate such that the isolation film is between the first semiconductor substrate and the second semiconductor substrate, the second semiconductor substrate comprising a second coil and a second contact pad;

placing the second semiconductor substrate on a lead frame;

connecting the first contact pad to the lead frame; and

connecting the second contact pad to the lead frame,

wherein disposing the isolation film comprises adhesive bonding an adhesive film comprising polyimide with a dielectric strength of 60 kV/mm to 100 kV/mm.

11. The method according to claim 10, wherein connecting the first contact pad to the lead frame comprises wire bonding the first contact pad to the lead frame and wherein connecting the second contact pad to the lead frame comprises wire bonding the second contact pad to the lead frame.

12. The method according to claim 10, further comprising thinning the first semiconductor substrate before forming the through via on the second side of the first semiconductor substrate.

13. A method of manufacturing a coreless transformer, the method comprising:

forming a first coil and a first contact pad on a first side of a first semiconductor substrate;

forming a through via on a second side of the first semiconductor substrate exposing the first contact pad;

disposing an isolation film on the first side of the first semiconductor substrate;

placing the first semiconductor substrate on a second semiconductor substrate such that the isolation film is between the first semiconductor substrate and the second semiconductor substrate, the second semiconductor substrate comprising a second coil and a second contact pad;

placing the second semiconductor substrate on a lead frame;

connecting the first contact pad to the lead frame; and

connecting the second contact pad to the lead frame,

wherein disposing the isolation film comprises adhesive pasting a polyimide film with a dielectric strength of 60 kV/mm to 100 kV/mm.

14. A method of manufacturing a coreless transformer, the method comprising:

forming a first coil and a first contact pad on a first side of a first semiconductor substrate;

forming a through via a second side of the first semiconductor substrate exposing the first contact pad;

disposing an isolation film on the first side of the first semiconductor substrate;

placing the first semiconductor substrate on a second semiconductor substrate such that the isolation film is between the first semiconductor substrate and the second semiconductor substrate, the second semiconductor substrate comprising a second coil and a second contact pad;

placing the second semiconductor substrate on a lead frame;

connecting the first contact pad to the lead frame; and

connecting the second contact pad to the lead frame,

wherein disposing the isolation film comprises adhesive pasting an epoxide film with a dielectric strength of 60 kV/mm to 100 kV/mm.