Memory apparatus and methods

• US 8,614,918 B2
• Filed: 05/02/2011
• Issued: 12/24/2013
• Est. Priority Date: 05/02/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/099,180
• Publication Number:
  US 20120281476A1
• Time in Patent Office: 967 Days
• Field of Search: 365/185.18
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Embodiments of apparatus and methods having a memory device can include a line to exchange information with a string of memory cells and a transistor coupled between the string of memory cells and the line. Such a memory device can also include a module configured to couple a gate of the transistor to a node during a first time interval of a memory operation and decouple the gate from the node during a second time interval of the memory operation. Additional apparatus and methods are described.

Claims

1. A memory device comprising:

a string of memory cells;

a line to exchange information with the string of memory cells;

a transistor coupled between the string of memory cells and the line; and

a module configured to couple a gate of the transistor to one of a first node having a voltage during a first time interval of a memory operation and a second node having a supply voltage of the device, and the module configured to decouple the gate of the transistor from the first node and the second node during a second time interval of the memory operation if no memory cell of the string is selected to be accessed during the memory operation.

2. The memory device of claim 1, wherein the module is configured to couple the gate of the transistor to another node during the second time interval if a memory cell of the string of memory cells is selected to be accessed during the memory operation.

3. The memory device of claim 1, wherein the the voltage at the first node during the first time interval includes a reference potential.

4. The memory device of claim 1, wherein the line is part of a data line of the memory device.

5. The memory device of claim 1, wherein the module is configured to couple the line to a voltage during the first time interval.

6. The memory device of claim 5, wherein the module is configured to decouple the line from the voltage during the second time interval.

7. The memory device of claim 6, further comprising:

an additional transistor coupled between the memory cells and a source line, wherein the module is configured to couple a gate of the additional transistor to a reference potential during the first time interval and to decouple the gate of the additional transistor from the reference potential during the second time interval.

8. A memory device comprising:

a string of memory cells;

a line to exchange information with the string of memory cells;

a transistor coupled between the string of memory cell and the line; and

a module configured to couple a gate of the transistor to a first node during a first time interval of a memory operation, to decouple the gate from the first node and couple the gate to a second node during a second time interval of the memory operation if a memory cell of the string is selected to be accessed during the memory operation, and to decouple the gate from the first and second nodes if no memory cell of the string is selected to be accessed during the memory operation.

9. The memory device of claim 8, wherein the first time interval comprises a charge time interval and the second time interval comprises a sensing time interval.

10. The memory device of claim 8, wherein the module is configured to sense information stored in a selected memory cell of the string in the memory operation.

11. The memory device of claim 8, wherein the first node is configured to receive a reference potential.

12. The memory device of claim 11, wherein the second node is configured to receive a voltage having a positive value.

13. A memory device comprising:

a string of memory cells;

a line to exchange information with the string of memory cells;

a first transistor to couple the string of memory cells to the line;

a second transistor to couple a gate of the first transistor to a first node during a first time interval of a memory operation, and the second transistor to decouple the gate of the first transistor from the first node during a second time interval of the memory operation; and

a third transistor to couple the gate of the first transistor to a second node during the second time interval if a memory cell of the string is selected to be accessed during the memory operation and not to couple the gate of the first transistor to the second node if no memory cell of the string is selected to be accessed during the memory operation.

14. The memory device of claim 13, wherein the line is part of a bit line of the memory device.

15. The memory device of claim 13, wherein the first time interval comprises a pre-charge time interval.

16. The memory device of claim 15, wherein the second time interval comprises a sensing time interval.

17. A memory device comprising:

a first group of memory cells and a second group of memory cells;

a line to exchange information with the first and second groups of memory cells;

a first transistor coupled between the line and the first group of memory cells;

a second transistor coupled between the line and the second group of memory cells; and

a module configured to access at least one memory cell of the first group of memory cells in a memory operation and to access none of the memory cells of the second group of memory cells in the memory operation, the module configured to couple a gate of the first transistor and a gate of the second transistor to a reference potential during a first time interval of the memory operation, and to couple the gate of the first transistor to a first voltage during a second time interval of the memory operation, and the module configured to decouple the gate of the second transistor from the reference potential and not to couple the gate of the second transistor to the first voltage during the second time interval of the memory operation.

18. The memory device of claim 17, wherein the module is configured to access at least one memory of the second group of memory cells in an additional memory operation and to access none of the memory cells of the first group of memory cells in the additional memory operation, the module configured to couple the gate of the first transistor and the gate of the second transistor to the reference potential during a first time interval of the additional memory operation, and to couple the gate of the second transistor to a second voltage during a second time interval of the additional memory operation, and the module configured to decouple the gate of the first transistor from the reference potential during the second time interval of the additional memory operation.

19. The memory device of claim 17, further comprising a substrate, wherein the first group of memory cell includes a first memory cell overlying the substrate and a second memory cell overlying the first memory cell.

20. The memory device of claim 17, wherein the first and second groups of memory cells are organized into pages, and the module is configured to store information in the pages in a non-sequential page order.

21. The memory device of claim 20, wherein at least one of the pages includes memory cells arranged in a same row.

22. The memory device of claim 20, wherein the non-sequential page order includes a random order.

23. A memory device comprising:

a first line and a second line;

a first device portion including a first plurality of memory cells coupled to the first line;

a second device portion including a second plurality of memory cells coupled to the second line;

a third line directly coupled to the first and second lines;

a data line; and

a switch to couple the data line to the third line, wherein the first device portion includes;

a string of memory cells;

a transistor coupled between the stringy of memory cells and the first line; and

a module configured to couple a gate of the transistor to one of a first node having voltage during a first time interval of a memory operation and a second node having a supply voltage of the device if a memory cell of the string is selected to be accessed during the memory operation, and the module configured to decouple the gate of the transistor from the first node and the second node during a second time interval of the memory operation if no memory cell of the string is selected to be accessed during the memory operation.

24. The memory device of claim 23, further comprising:

a fourth line;

a third device portion including a third plurality of memory cells coupled to the fourth line; and

an additional switch to couple the data line to the fourth line.

25. The memory device of claim 24, wherein the switch includes a transistor having a first node directly coupled to the third line and a second node directly coupled to the data line.

26. A method comprising:

coupling a gate of a transistor coupled between a data line and a string of memory cells to a node during a first time interval of a memory operation, the node includes a ground node;

decoupling the gate of the transistor from the node during a second time interval of the memory operation;

coupling the of the transistor to a different node during the second time interval if a memory cell of the string is selected to be accessed during the memory operation; and

not coupling the gate of the transistor to the different node during the second time interval if no memory cell of the string is selected to be accessed during the memory operation.

27. The method of claim 26, wherein the different node is configured to receive a voltage having a positive value.

28. A method comprising:

applying a reference potential to a gate of a transistor during a first time interval of a memory operation, the transistor coupled between a string of memory cells of a memory device and a line used to exchange information with the string of memory cells;

coupling the string of memory cell to the line through the transistor during a second time interval of the memory operation if a memory cell of the string is selected to be accessed during the second time interval, wherein coupling the string of memory cells includes applying a first voltage to the gate of the transistor; and

decoupling the string of memory cells from the line if no memory cell of the string is selected to be accessed during the second time interval, wherein decoupling the string of memory cells includes decoupling the gate of the transistor from the reference potential and to coupling the gate of the transistor to the first voltage.

29. The method of claim 28, further comprising:

coupling the line to a second voltage when the gate of the transistor is coupled to the reference potential.

30. The method of claim 29, further comprising:

decoupling the line from the second voltage when the gate of the transistor is coupled to the first voltage.