Memory modules with reliability and serviceability functions

• US 8,615,679 B2
• Filed: 09/14/2012
• Issued: 12/24/2013
• Est. Priority Date: 06/24/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Smith, Michael John Sebastian, Rajan, Suresh Natarajan
• Primary Examiner(s): PATEL, KAMINI B
• Application Number:
  US13/618,246
• Publication Number:
  US 20130132779A1
• Time in Patent Office: 466 Days
• Field of Search: 714/5.1
• US Class Current: 714/5.1
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/26 Functional testing
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 17/00 Digital computing or data processing equipment or methods, specially adapted for specific functions information retrieval, database structures or file system structures therefor G06F16/00
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/12 : Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Claims

1. A memory module comprising:

a plurality of memory chips comprising a first memory chip and a second memory chip;

a plurality of intelligent buffer chips comprising;

a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and

a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;

an intelligent register chip coupled to a memory controller; and

a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips,

wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.

2. The memory module of claim 1, further comprising:

a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to;

receive the first data and the second data from the intelligent register chip;

store the first data and the second data; and

provide the first data and the second data to the memory controller.

3. The memory module of claim 1, wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.

4. The memory module of claim 1, wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.

5. The memory module of claim 4, wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.

6. The memory module of claim 1, wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.

7. The memory module of claim 1, wherein the intelligent register chip is configured to perform a self-test on the memory module.

8. A memory module comprising:

a plurality of memory chips comprising a first memory chip and a second memory chip;

a plurality of intelligent buffer chips comprising;

a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and

a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;

an intelligent register chip coupled to a memory controller;

a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips;

a first data bus coupling the intelligent register chip and the first memory chip; and

a second data bus coupling the intelligent register chip and the second memory chip,

wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.

9. The memory module of claim 8, further comprising:

a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to;

receive the first data and the second data from the intelligent register chip;

store the first data and the second data; and

provide the first data and the second data to the memory controller.

10. The memory module of claim 8, wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.

11. The memory module of claim 8, wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.

12. The memory module of claim 11, wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.

13. The memory module of claim 8, wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.

14. The memory module of claim 8, wherein the intelligent register chip is configured to perform a self-test on the memory module.

15. A memory module comprising:

a plurality of memory chips comprising a first memory chip and a second memory chip;

a plurality of intelligent buffer chips comprising;

a first intelligent buffer chip coupled to the first memory chip, wherein the first intelligent buffer chip includes a first temperature monitoring device configured to perform temperature measurements of the first memory chip; and

a distinct second intelligent buffer chip coupled to the second memory chip, wherein the second intelligent buffer chip includes a second temperature monitoring device configured to perform temperature measurements of the second memory chip;

an intelligent register chip coupled to a memory controller;

a sideband bus coupling the intelligent register chip and the plurality of intelligent buffer chips;

a first data bus coupling the memory controller and the first memory chip; and

a second data bus coupling the memory controller and the second memory chip,

wherein the intelligent register chip is configured to receive (i) from the first intelligent buffer chip via the sideband bus, first data representing the temperature measurements of the first memory chip and (ii) from the second intelligent buffer chip via the sideband bus, second data representing the temperature measurements of the second memory chip.

16. The memory module of claim 15, further comprising:

a serial presence detect (SPD) chip coupled to the memory controller and the intelligent register chip, the SPD chip configured to;

receive the first data and the second data from the intelligent register chip;

store the first data and the second data; and

provide the first data and the second data to the memory controller.

17. The memory module of claim 15, wherein the first intelligent buffer chip and the first memory chip form a first stack on the memory module, and the second intelligent buffer chip and the second memory chip form a second stack on the memory module.

18. The memory module of claim 15, wherein the intelligent register chip is configured to issue commands via the sideband bus to reduce power consumption of the first intelligent buffer chip.

19. The memory module of claim 18, wherein the intelligent register chip is configured to turn off an output buffer of the first intelligent buffer chip.

20. The memory module of claim 15, wherein the first intelligent buffer chip is configured to control a light-emitting diode to indicate a failure of the memory module.