High reliability processor system
First Claim
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1. A computer system comprising:
- a processor executing a stored program, the processor providing for an execution of instructions on the processor, the stored program executing on the processor to;
(a) perform functions of a first application program employing at least a subset of the instructions;
(b) perform a calculation employing the subset of the instructions, the calculation provoking an error state of the processor when any of the subset of the instructions is not operating correctly, the calculation further entering a predetermined delay loop when the results of a given instruction in the calculation are incorrect;
wherein the processor includes a timer triggering an error state at a conclusion of a predetermined time and wherein the calculation is performed repeatedly at a period less than the predetermined time and wherein the processor resets the timer using at least one instruction in the subset of instructions only when the result of the calculation matches a correct output value and wherein the correct output value provides an address of a memory mapped reset of the timer used by the processor to reset the timer.
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Abstract
A method of testing the integrity of microprogramming within a computer processor employs a test calculation designed to exercise instructions and to reveal errors in those instructions. The problem of testing instructions using the very instructions which may possibly be corrupt is addressed by developing a signature passed from instruction to instruction providing a low likelihood of a false positive outcome. A time-out system is used in the evaluation of the test calculation to capture a wide variety of other pathological operating conditions.
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Citations
13 Claims
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1. A computer system comprising:
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a processor executing a stored program, the processor providing for an execution of instructions on the processor, the stored program executing on the processor to; (a) perform functions of a first application program employing at least a subset of the instructions; (b) perform a calculation employing the subset of the instructions, the calculation provoking an error state of the processor when any of the subset of the instructions is not operating correctly, the calculation further entering a predetermined delay loop when the results of a given instruction in the calculation are incorrect; wherein the processor includes a timer triggering an error state at a conclusion of a predetermined time and wherein the calculation is performed repeatedly at a period less than the predetermined time and wherein the processor resets the timer using at least one instruction in the subset of instructions only when the result of the calculation matches a correct output value and wherein the correct output value provides an address of a memory mapped reset of the timer used by the processor to reset the timer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 11, 12)
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9. A computer system comprising:
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a processor executing a stored program, the processor providing for an execution of instructions on the processor, the stored program executing on the processor to; (a) perform functions of a first application program employing at least a subset of the instructions; (b) perform a calculation employing the subset of the instructions to calculate a value, the calculation provoking an error state of the processor when any of the subset of the instructions is not operating correctly; wherein the calculation enters a predetermined delay loop when data results of a given instruction or flag results of a given instruction in the calculation are incorrect; wherein a correct value of the calculation provides an address of a memory mapped reset of a timer used by the processor to reset a timer, the timer triggering an error state at a conclusion of a predetermined time; and wherein the processor resets the timer using at least one instruction in the subset of instructions. - View Dependent Claims (10)
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13. A method of testing a processor of a type providing for the execution of instructions on the processor, the method comprising the steps of:
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(a) performing the functions of a first application program employing at least a subset of the instructions; (b) performing a calculation employing the subset of the instructions, the calculation providing a predetermined value when the subset of instructions is properly operating; (c) provoking an error state of the processor when the calculation provides a value different from the predetermined value and by entering a predetermined delay loop when data results of a given instruction or flag results of a given instruction in the calculation are incorrect; (d) wherein the processor includes a timer triggering an error state at a conclusion of a predetermined time and wherein the calculation is performed repeatedly at a period less than the predetermined time and wherein the processor resets the timer using at least one instruction in the subset of instructions, wherein the predetermined value provides an address of a memory mapped reset of the timer used by the processor to reset the timer; and wherein the processor resets the timer using at least one instruction in the subset of instructions.
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Specification