Process for improving design-limited yield by localizing potential faults from production test data

• US 8,615,691 B2
• Filed: 03/06/2007
• Issued: 12/24/2013
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Dokken, Richard C, Chan, Gerald S., Crouch, Alfred L, Potter, John C
• Primary Examiner(s): Bhatia, Ajay
• Assistant Examiner(s): GANDHI, DIPAKKUMAR B
• Application Number:
  US11/682,314
• Publication Number:
  US 20080091981A1
• Time in Patent Office: 2,485 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Claims

1. A method for reporting a physical area containing an electrically detected fault in a scan chain bit position recorded on semiconductor test equipment apparatus to a computer-implemented yield management utility software program product comprising the following steps:

localizing the electrically detected fault in the scan chain bit position to within a detailed physical circuit description;

tracing circuit structures that are connected to a scan cell with which the electrically detected fault in the scan chain bit position is associated; and

in response to the tracing, determining and exporting X/Y Die Coordinate on Wafer, X/Y Origin on Die, X size, Y size, Area (X*Y) and Classification of potential sources of the electrically detected fault in the scan chain bit position.

2. A computer-implemented method, comprising:

translating a fault location in a circuit from i) a scan chain bit position, to ii) a name of a scan cell in a logical design;

using the name of the scan cell to execute a trace of circuit structures that are connected to the scan cell, thereby identifying circuit structures that are potential sources of faults in the circuit; and

reporting physical locations of the circuit structures.

3. The computer-implemented method of claim 2, wherein reporting the physical locations of the circuit structures comprises:

displaying the physical locations of the circuit structures.

4. The computer-implemented method of claim 2, wherein reporting physical locations of the circuit structures comprises:

computing a bounding box having minimum and maximum coordinate values of the physical locations of the circuit structures.

5. The computer-implemented method of claim 2, wherein the reported physical locations are locations on a die.

6. The computer-implemented method of claim 2, wherein the reported physical locations are locations on a wafer.

7. The computer-implemented method of claim 2, wherein using the name of the scan cell to execute a trace of circuit structures that are connected to the scan cell comprises:

executing a trace of circuit structures that fan-in to the scan cell.

8. The computer-implemented method of claim 2, wherein using the name of the scan cell to execute a trace of circuit structures that are connected to the scan cell comprises:

executing a trace of circuit structures that fan-out of the scan cell.

9. The computer-implemented method of claim 2, wherein using the name of the scan cell to execute a trace of circuit structures that are connected to the scan cell comprises:

executing a tree-trace of clock delivery circuit structures for the scan cell.

10. The computer-implemented method of claim 2, further comprising:

saving information on each executed trace;

repeating said method for a same or different fault location; and

during said repeating of the method, checking for saved information on an executed trace, and using the saved information in lieu of re-executing a trace.

11. The computer-implemented method of claim 2, further comprising:

determining a class of fault corresponding to the fault location; and

using the name of the scan cell to execute a particular type of trace of circuit structures, the particular type of trace being based on the class of fault.

12. The computer-implemented method of claim 2, further comprising:

setting limits on the circuit structures identified by the trace.

13. The computer-implemented method of claim 2, wherein using the name of the scan cell to execute a trace of circuit structures that are connected to the scan cell comprises:

parsing at least one LEF file and at least one DEF file.