Stacking fault and twin blocking barrier for integrating III-V on Si

• US 8,617,945 B2
• Filed: 02/03/2012
• Issued: 12/31/2013
• Est. Priority Date: 08/02/2006
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hudait, Mantu K., Shaheen, Mohamad A., Chow, Loren A., Tolchinsky, Peter G., Fastenau, Joel M., Loubychev, Dmitri, Liu, Amy W. K.
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US13/366,143
• Publication Number:
  US 20120142166A1
• Time in Patent Office: 697 Days
• Field of Search: 257/190, 257/200, 257/201, 257/615, 257/E21.09, 257/E21.097, 257/E21.098, 257/E21.108, 257/E21.109, 257/E21.112, 438/46, 438/47, 438/93, 438/94, 438/172, 438/191, 438/938
• US Class Current: 438/172
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02466 Antimonides
• CPC Class Codes: H01L 21/02549 Antimonides
• CPC Class Codes: H01L 21/02617 Deposition types
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer

Abstract

A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10⁸ cm⁻² to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

Claims

1. A method of forming a semiconductor structure comprising:

depositing a nucleation layer comprising Ga and Sb using migration enhanced epitaxy (MEE) at a first growth temperature and first growth rate of approximately 0.1 um/hr on a surface of a silicon substrate,

depositing a buffer layer consisting essentially of GaSb at a second growth temperature and second growth rate on the nucleation layer; and

forming a compound semiconductor device layer directly on the buffer layer;

wherein the second growth temperature is higher than the first growth temperature.

2. The method of claim 1, wherein the surface is a (100) surface of the silicon substrate off-cut at an angle between 2 and 12 degrees towards a [110] direction.

3. The method of claim 1, wherein the surface is off-cut from a plane selected from the group consisting of:

(211), (511), (711), (013).

4. The method of claim 1, wherein forming the compound semiconductor device layer upon the buffer layer further comprises depositing InSb at a growth temperature between approximately 300°

C. and 500°

C.

5. The method of claim 1, wherein the surface of the silicon substrate upon which the nucleation layer is deposited is a vicinal surface comprising terraces, and wherein depositing the nucleation layer includes depositing alternating monolayers of Sb and Ga until the nucleation layer is sufficiently thick to fill substantially all the terraces of the vicinal surface.

6. The method of claim 1, wherein the first growth temperature is between approximately 300°

C. and 600°

C.

7. The method of claim 1, wherein the second growth temperature is approximately 510°

C.

8. The method of claim 1, wherein depositing the nucleation layer comprising Ga and Sb using migration enhanced epitaxy (MEE) comprises iterations of the following sequence:

exposing the substrate to a Sb source, shuttering the Sb source, applying an approximately 60 second hold time in which both the Sb source and a Ga source are shuttered, exposing the substrate to the Ga source, shuttering the Ga source, and applying no hold time in which both the Sb source and the Ga source are shuttered.

9. A method of forming a compound semiconductor device layer on a silicon substrate comprising:

depositing GaSb upon a surface of the silicon substrate using migration enhanced epitaxy (MEE) at a first growth temperature and first growth rate of approximately 0.1 um/hr to form a GaSb nucleation layer, wherein the surface of the silicon substrate is off-cut from a (100) surface at an angle between 2 and 12 degrees toward a [110] direction;

depositing GaSb upon the GaSb nucleation layer at a second growth temperature and second growth rate to form a GaSb buffer layer, wherein the second growth temperature is higher than the first growth temperature; and

depositing an InSb device layer directly on the GaSb buffer layer.

10. The method of claim 9, wherein depositing GaSb upon the surface of the silicon substrate using migration enhanced epitaxy (MEE) at the first growth temperature and first growth rate to form the GaSb nucleation layer comprises iterations of the following sequence:

exposing the silicon substrate to a Sb source, shuttering the Sb source, applying an approximately 60 second hold time in which both the Sb source and a Ga source are shuttered, exposing the silicon substrate to the Ga source, shuttering the Ga source, and applying no hold time in which both the Sb source and the Ga source are shuttered.