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Stacking fault and twin blocking barrier for integrating III-V on Si

  • US 8,617,945 B2
  • Filed: 02/03/2012
  • Issued: 12/31/2013
  • Est. Priority Date: 08/02/2006
  • Status: Expired due to Fees
First Claim
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1. A method of forming a semiconductor structure comprising:

  • depositing a nucleation layer comprising Ga and Sb using migration enhanced epitaxy (MEE) at a first growth temperature and first growth rate of approximately 0.1 um/hr on a surface of a silicon substrate,depositing a buffer layer consisting essentially of GaSb at a second growth temperature and second growth rate on the nucleation layer; and

    forming a compound semiconductor device layer directly on the buffer layer;

    wherein the second growth temperature is higher than the first growth temperature.

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