Memory having a vertical access device

• US 8,617,953 B2
• Filed: 12/13/2010
• Issued: 12/31/2013
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US12/966,582
• Publication Number:
  US 20110081757A1
• Time in Patent Office: 1,114 Days
• Field of Search: 438/270, 438/589, 257329-334, 257/E21.176, 257/E21.214
• US Class Current: 438/270
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.

Claims

1. A method of forming a memory device structure, comprising:

providing recesses in a substrate, each recess having a pair of opposed side walls and a floor extending between the opposed side walls;

depositing a dielectric on the side walls and the floor of each recess;

forming a conductive film on the dielectric;

processing the conductive film to remove the conductive film from the floor of each recess and to remove at least a portion of the conductive film from the opposed sidewalls of each recess; and

providing trenches between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposed side walls of the recesses, and having a depth greater than a depth of the recesses.

2. The method of claim 1, further comprising providing other trenches between adjacent ones of the recesses, substantially in parallel with the recesses, and having a depth greater than the depth of the recesses.

3. The method of claim 1, wherein providing the recesses further comprises etching the recesses to a depth of approximately about 1.5 F, where F is a relevant feature size of a memory device that includes the memory device structure.

4. The method of claim 3, wherein etching the recesses to a depth of approximately 1.5 F further comprises etching the recesses to a depth of approximately 1750 angstroms (Å

).

5. The method of claim 1, wherein depositing the dielectric on the side walls and the floor of each recess further comprises growing one of silicon dioxide or silicon nitride.

6. The method of claim 1, wherein forming the conductive film on the dielectric further comprises depositing the conductive film to a thickness that ranges between approximately 0.25 F and approximately 0.5 F, where F is a relevant feature size of the memory device.

7. The method of claim 6, wherein depositing the conductive film to a thickness that ranges between approximately 0.25 F and approximately 0.5 F further comprises depositing the conductive film to a thickness that ranges between approximately 150 angstroms (Å

) to approximately 350 angstroms (Å

).

8. The method of claim 1, wherein forming the conductive film on the dielectric further comprises depositing one of a metal, a polysilicon, a titanium nitride (TiN), a tantalum nitride (TaNi), a cobalt silicide (CoSi) or a nickel silicide (NiSi).

9. The method of claim 1, wherein processing the conductive film further comprises:

depositing an auxiliary layer on the conductive film;

spacer-etching the auxiliary layer and the conductive film to remove the auxiliary layer and the conductive film from the floor of each recess; and

undercutting portions of the conductive film positioned between the auxiliary layer and the dielectric layer adjacent to the sidewalls to obtain a selected operating characteristic.

10. The method of claim 9, further comprising removing portions of the auxiliary layer adjacent to the sidewalls.

11. The method of claim 1, further comprising providing active areas in the structure by forming regions having a selected conductivity adjacent to the conductive film.

12. The method of claim 11, wherein providing active areas in the structure by forming regions having a selected conductivity further comprises forming regions having an n-conductivity.

13. The method of claim 11, wherein providing active areas in the structure by forming regions having a selected conductivity further comprises forming regions having an p-conductivity.

14. The method of claim 1, further comprising providing active areas in the structure by providing a first region having a first conductivity, and a second region having a second conductivity, wherein the first conductivity is different from the second conductivity.

15. The method of claim 1, further comprising forming a conductive gate structure in each recess by depositing a conductive material in each recess, and coupling the conductive gate structure to a conductive wordline structure.

16. A method of forming a memory device structure, comprising:

providing recesses in a substrate, each recess having a pair of opposed side walls and a floor extending between the opposed side walls;

depositing a dielectric on the side walls and the floor of each recess;

forming a conductive film on the dielectric;

processing the conductive film to remove the conductive film from the floor of each recess and to remove at least a portion of the conductive film from the opposed side walls;

providing trenches between adjacent ones of the recesses, substantially in parallel with the recesses, and having a depth greater than a depth of the recesses; and

providing other trenches between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposed side walls of the recesses, and having a depth greater than a depth of the recesses.

17. A method of forming a memory device structure, comprising:

providing recesses in a substrate, each recess having a pair of opposed side walls and a floor extending between the opposed side walls;

depositing a dielectric on the side walls and the floor of each recess;

forming a conductive film on the dielectric;

processing the conductive film to remove the conductive film from the floor of each recess and to remove at least a portion of the conductive film from the opposed side walls of each recess, wherein each recess extends into the substrate to a recess depth, and the conductive film extends along respective side walls of each recess to a conductive film depth that is less than the recess depth; and

providing trenches between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposed side walls of the recesses, and having a depth greater than a depth of the recesses.

18. The method of claim 17, wherein the conductive film is formed to have a lower edge that extends away from an intersection of the side walls and the floor of each recess.

19. The method of claim 17, wherein the dielectric is deposited to have a trench dielectric layer that substantially covers the floor and the pair of opposing side walls of each recess.