Silicon microphone transducer

• US 8,617,960 B2
• Filed: 12/16/2010
• Issued: 12/31/2013
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Denison, Marie, Goodlin, Brian E., Shih, Wei-Yan, Barron, Lance W.
• Primary Examiner(s): OLSEN, ALLAN W
• Application Number:
  US12/969,784
• Publication Number:
  US 20110158439A1
• Time in Patent Office: 1,111 Days
• Field of Search: None
• US Class Current: 438/396
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence

Abstract

A capacitive microphone transducer integrated into an integrated circuit includes a fixed plate and a membrane formed in or above an interconnect region of the integrated circuit. A process of forming an integrated circuit containing a capacitive microphone transducer includes etching access trenches through the fixed plate to a region defined for the back cavity, filling the access trenches with a sacrificial material, and removing a portion of the sacrificial material from a back side of the integrated circuit.

Claims

1. A process of forming an integrated circuit containing a capacitive microphone transducer, comprising the steps:

providing a substrate in which said substrate includes a base layer, an etch stop layer formed on said base layer, and a top layer formed on said etch stop layer;

forming a first interconnect region on a top surface of said substrate;

forming a fixed plate on a top surface of said first interconnect region;

forming access trenches through said first interconnect region into said substrate;

in which said step of forming said access trenches is performed so that said access trenches extend through said top layer;

forming a sacrificial fill region of sacrificial material above said fixed plate;

forming a first membrane layer on a top surface of said sacrificial fill region;

forming a sacrificial protective layer of sacrificial material over a top surface of said first membrane layer;

forming a backside cavity in said substrate, said backside cavity extending from a bottom surface of said substrate to said access trenches;

in which said step of forming said backside cavity is performed so that said backside cavity extends through said base layer;

removing a portion of said sacrificial material in said access trenches by a process of etching from a back side of said integrated circuit; and

removing said sacrificial material from said sacrificial fill region.

2. The process of claim 1, in which said first membrane layer is formed concurrently with liner metal elements of interconnects in said integrated circuit.

3. The process of claim 1, in which said first membrane layer is selected from the group consisting of tantalum nitride, titanium nitride, titanium aluminum, aluminum, aluminum with copper, silicon nitride, silicon oxy-nitride, silicon carbide, silicon nitride carbide, and silicon oxy-nitride carbide.

4. The process of claim 1, in which said first membrane layer is formed so as to include a stress relief configuration.

5. The process of claim 1, further including forming a second membrane layer on a top surface of said first membrane layer, so that lateral edges of a main portion of said second membrane layer do not extend to lateral edges of said first membrane layer.

6. The process of claim 5, in which said second membrane layer is formed concurrently with elements of interconnects in said integrated circuit.

7. The process of claim 6, in which said second membrane layer is selected from the group consisting of copper, aluminum, and aluminum with copper.

8. The process of claim 1, in which said fixed plate is formed concurrently with elements of interconnects in said integrated circuit.

9. A process of forming an integrated circuit including a movable membrane, comprising:

forming an interconnect layer for interconnecting underlying circuit elements over a substrate;

forming a first conductive material layer over the interconnect layer;

patterning the first conductive layer to define a first capacitor plate positioned between and separated from second capacitor plate terminal contact points, and to form at least one cavity access opening through the capacitor plate;

selectively etching the interconnect layer through the at least one cavity access opening to form a corresponding at least one access trench down to the substrate;

forming a sacrificial layer over the patterned first conductive layer including over the first capacitor plate and the second capacitor plate terminal contact points and extending into the at least one trench;

patterning the sacrificial layer to expose the second capacitor plate terminal contact points peripherally of the first capacitor plate;

forming a second conductive material layer over the patterned sacrificial layer to define a second capacitor plate having a first portion spaced above the first capacitor plate and a second portion peripheral to the first portion extending down into contact with the exposed second capacitor plate terminal contact points;

forming a third conductive material layer on the second conductive material layer at least in the first portion of the second capacitor plate;

the third conductive material layer having a main portion in contact with the first portion of the second capacitor plate but laterally spaced from the second portion of the second capacitor plate;

forming an opening which connects to the trenches in a backside of the substrate; and

removing at least enough of the sacrificial layer to define a cavity between the first portion of the second conductive material and the first capacitor plate in communication with the backside cavity through the cavity access openings and in which the first portion of the second capacitor plate may move in electrical attraction to or repulsion from the first capacitor plate;

the second capacitor plate being dimensioned and configured to allow such movement.

10. The process of claim 9, further comprising patterning the second and third conductive material layers to define openings through the first portion of the second capacitor plate in communication with the cavity between the first portion and the first capacitor plate.

11. The process of claim 9, further comprising forming the second conductive material layer to provide a stress relief configuration between the first and second portions of the second capacitor plate.

12. The process of claim 9, further comprising forming the second conductive material layer to provide corrugations between the first and second portions of the second capacitor plate.

13. The process of claim 9, further comprising forming a second sacrificial layer over the second and third conductive material layers prior to forming the opening in the backside of the substrate;

and removing the second sacrificial layer after forming the opening in the backside of the substrate.

14. A process of forming an integrated circuit including a movable membrane, comprising:

forming an interconnect layer for interconnecting underlying circuit elements over a substrate;

forming a first conductive material layer over the interconnect layer;

patterning the first conductive layer to define a first capacitor plate positioned between and separated from second capacitor plate terminal contact points, and to form at least one cavity access opening through the capacitor plate;

selectively etching the interconnect layer through the at least one cavity access opening to form a corresponding at least one access trench down to the substrate;

forming a sacrificial layer over the patterned first conductive layer including over the first capacitor plate and the second capacitor plate terminal contact points and extending into the at least one trench;

patterning the sacrificial layer to expose the second capacitor plate terminal contact points peripherally of the first capacitor plate;

forming a second conductive material layer over the patterned sacrificial layer to define a second capacitor plate having a first portion spaced above the first capacitor plate and a second portion peripheral to the first portion extending down into contact with the exposed second capacitor plate terminal contact points;

further comprising forming the second conductive material layer to provide a stress relief configuration between the first and second portions of the second capacitor plate;

forming a third conductive material layer on the second conductive material layer at least in the first portion of the second capacitor plate;

wherein the third conductive material layer is also formed on the second conductive material layer in the second portion of the second capacitor plate but not at the stress relief configuration;

forming an opening which connects to the trenches in a backside of the substrate; and

removing at least enough of the sacrificial layer to define a cavity between the first portion of the second conductive material and the first capacitor plate in communication with the backside cavity through the cavity access openings and in which the first portion of the second capacitor plate may move in electrical attraction to or repulsion from the first capacitor plate;

the second capacitor plate being dimensioned and configured to allow such movement.

15. A process of forming an integrated circuit including a movable membrane, comprising:

forming an interconnect layer for interconnecting underlying circuit elements over a substrate;

forming a first conductive material layer over the interconnect layer;

patterning the first conductive layer to define a first capacitor plate positioned between and separated from second capacitor plate terminals, and to form cavity access openings through the capacitor plate;

selectively etching the interconnect layer through the cavity access openings to form corresponding access trenches down to the substrate;

forming a first sacrificial layer over the patterned first conductive layer including over the first capacitor plate and the second capacitor plate terminals and extending into the trenches;

patterning the first sacrificial layer to form vias peripherally of the first capacitor plate down to and exposing the second capacitor plate terminals;

forming a second conductive material layer over the patterned first sacrificial layer to define a second capacitor plate having a first portion spaced above the first capacitor plate and a second portion peripheral to the first portion extending down into the vias into contact with the exposed second capacitor plate terminals, wherein the second conductive material layer is formed with a stress relief configuration between the first and second portions of the second capacitor plate;

forming a third conductive material layer on the second conductive material layer over the first and second portions of the second capacitor plate including extending down into the vias, the third conductive material layer not present over the stress relief configuration;

forming an opening which connects to the trenches in a backside of the substrate; and

removing the first sacrificial layer to define a cavity between the first portion of the second conductive material and the first capacitor plate in communication with the backside cavity through the cavity access openings and in which the first portion of the second capacitor plate may move in electrical attraction to or repulsion from the first capacitor plate;

the second capacitor plate being dimensioned and configured to allow such movement.