Through hole via filling using electroless plating

• US 8,617,987 B2
• Filed: 12/30/2010
• Issued: 12/31/2013
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Gan, Kah Wee, Jin, Yonggang, Liu, Yun, Huang, Yaohuang
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/982,697
• Publication Number:
  US 20120168942A1
• Time in Patent Office: 1,097 Days
• Field of Search: 438/106, 438/107, 438/109, 438/653, 438/667, 257/E21.584, 257/E21.499, 257/E23.069, 257/E25.012, 257/E25.013
• US Class Current: 438/667
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15747 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating.

Claims

1. A method comprising:

forming an aperture in a substrate;

attaching an integrated circuit die to the substrate;

depositing a first layer of conductive material in the aperture and on a contact pad of the integrated circuit die by physical vapor deposition;

depositing a second layer of conductive material in the aperture and on the contact pad by electroless plating; and

depositing a third layer of conductive material in the aperture and on the contact pad by electroplating.

2. The method of claim 1, further comprising depositing a barrier layer in the aperture prior to depositing the first layer of conductive material.

3. The method of claim 2 wherein the barrier layer is formed of a material selected from a group consisting of TiW, Ti, Cr, TiN, and TaN.

4. The method of claim 1, further comprising filling the aperture with a dielectric material.

5. The method of claim 1 wherein the first layer of conductive material is copper.

6. The method of claim 1 wherein the second and third layers of conductive material are copper.

7. A method comprising:

attaching a first integrated circuit die to a substrate;

forming an aperture in a substrate;

forming a first layer of copper in the aperture and on a contact pad of the integrated circuit die;

forming a second layer of copper in the aperture and on the contact pad;

forming a third layer of copper in the aperture and on the contact pad;

placing a first solder ball on over a first surface of the substrate; and

electrically connecting the solder ball to the first layer of copper.

8. The method of claim 7 comprising:

placing a second integrated circuit over a second surface of the substrate; and

electrically connecting a contact pad of the second integrated circuit to the first layer of copper.

9. The method of claim 7 wherein a second solder ball is between the second integrated circuit and the second surface of the substrate, the second solder ball being electrically connected to the contact pad of the second integrated circuit.