Liner property improvement

• US 8,617,989 B2
• Filed: 04/19/2012
• Issued: 12/31/2013
• Est. Priority Date: 09/26/2011
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sapre, Kedar, Hernandez, Manuel, Luo, Lei
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US13/451,207
• Publication Number:
  US 20130102149A1
• Time in Patent Office: 621 Days
• Field of Search: 257/E23.067, 257/E23.174, 257/E21.275, 257/E21.597, 438/667, 438/763, 438/784
• US Class Current: 438/667
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall.

Claims

1. A method of processing a semiconductor substrate having a field region and at least one via defined by sidewalls and having a depth greater than 1 μ

m, the method comprising;

depositing a lining layer comprising silicon, oxygen, and phosphorus and having a varying thickness of between about 50 nm and about 500 nm along the sidewalls of the via such that a first thickness of the liner layer at an upper portion of the via sidewall is less than about 5 times a second thickness of the liner layer at a lower portion of the via sidewall.

2. The method of claim 1, wherein the phosphorus is deposited from a precursor comprising triethylphosphate (TEPO) or phosphine.

3. The method of claim 1, wherein the amount of phosphorus in the lining layer is 4 percent by weight.

4. The method set forth in claim 1, wherein the lining layer includes a bulk layer and a capping layer at least one of which is a phosphorus-doped silicon oxide layer.

5. The method of claim 1, further comprising depositing a barrier layer after the lining layer.

6. The method of claim 1, wherein the thickness of the lining layer is between about 100 nanometers and about 200 nanometers at all locations along the liner layer within the at least one via.

7. The method of claim 1, wherein the thickness of the lining layer at the lower portion of the via sidewall is at least about 20% of the thickness of the deposited material on the field region of the semiconductor substrate.

8. The method of claim 1, wherein the thickness of the lining layer at the lower portion of the via sidewall is at least about 25% of the thickness of the deposited material in the field region of the semiconductor substrate.

9. The method of claim 1, wherein the thickness of the lining layer at the lower portion of the via sidewall is at least about 30% of the thickness of the lining layer at the upper portion of the via sidewall.

10. The method of claim 1, wherein the forming of the lining layer is performed at a temperature that is less than or about 400°

C.

11. A method of forming a through-silicon via structure (TSV) on a semiconductor substrate, the method comprising:

providing the semiconductor substrate having a plurality of transistors with a minimum feature size formed thereon and at least one via defined by sidewalls, the at least one via having a width that is at least two orders of magnitude greater than the minimum feature size of the transistors and a depth that is at least three orders of magnitude greater than the minimum feature size; and

depositing a lining layer comprising silicon, oxygen, and phosphorus and having a varying thickness of between about 50 nm and about 500 nm along the sidewalls of the via such that a first thickness of the liner layer at an upper portion of the via sidewall is less than about 5 times a second thickness of the liner layer at a lower portion of the via sidewall.

12. The method of claim 11, wherein the lining layer includes a bulk layer and a capping layer at least one of which is a phosphorus-doped silicon oxide layer.

13. The method of claim 12, wherein the bulk layer is doped with phosphorus, but the capping layer is not.

14. The method of claim 12, wherein the capping layer is doped with phosphorus, but the bulk oxide layer is not.

15. The method of claim 11, wherein the phosphorus is deposited using triethylphosphate (TEPO).

16. The method of claim 11, wherein forming the lining layer occurs at a temperature of the semiconductor substrate that is less than or about 400°

C.

17. The method of claim 11, wherein forming the lining layer also deposits material on the field region of the semiconductor substrate, and wherein the thickness of the lining layer at the lower portion of the via sidewall is at least about 25% of the thickness of the deposited material in the field region of the semiconductor substrate.

18. The method of claim 11, wherein the thickness of the lining layer at the lower portion of the via sidewall is at least about 30% of the thickness of the lining layer at the upper portion of the via sidewall.

19. The method of claim 11, wherein the thickness of the lining layer is between about 100 nanometers and about 200 nanometers at all locations along the liner layer within the at least one via.

20. The method of claim 11, wherein the amount of doping in the lining layer is about 2 percent by weight or about 4 percent by weight, or at some percentage there between.