Fin removal method

• US 8,617,996 B1
• Filed: 01/10/2013
• Issued: 12/31/2013
• Est. Priority Date: 01/10/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Chi, Min-hwa, Shen, Honglian, Xiao, Changyong
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/738,435
• Time in Patent Office: 355 Days
• Field of Search: 257/E21.014, 257/E21.37, 257/E21.377, 257/E21.4
• US Class Current: 438/700
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods for removal of fins from a semiconductor structure are provided. A fin liner is applied to the fins. The fin liner is then removed from the fins that are to be removed. The fin liner is of a material that is selective compared to the semiconductor fins. Hence, the fins can be removed without significant damage to the fin liner. The subsets of fins that are to be removed are then removed, while the fin liner protects the adjacent fins that are to be kept.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a plurality of semiconductor fins disposed on a semiconductor substrate;

depositing a fin liner on the plurality of semiconductor fins;

removing the fin liner from a subset of semiconductor fins of the plurality of semiconductor fins;

depositing a silicon-based gap fill material on the plurality of semiconductor fins; and

removing the silicon-based gap fill material and the subset of semiconductor fins.

2. The method of claim 1, wherein removing the silicon-based gap fill material and the subset of semiconductor fins is performed with an isotropic etch process.

3. The method of claim 2, wherein removing the silicon-based gap fill material and the subset of semiconductor fins is performed with a wet etch process.

4. The method of claim 2, wherein the isotropic etch process is performed using hydrofluoric acid.

5. The method of claim 2, wherein the isotropic etch process is performed using tetramethylammonium hydroxide.

6. The method of claim 1, wherein depositing a fin liner comprises depositing an enhanced high aspect ratio process (eHARP) oxide.

7. The method of claim 1, wherein depositing a fin liner comprises depositing silicon oxide via atomic layer deposition.

8. The method of claim 1, further comprising depositing a second gap fill material comprised of the same material as the fin liner.

9. A method of fabricating a semiconductor structure, comprising:

forming a plurality of semiconductor fins disposed on a semiconductor substrate;

depositing a fin liner on the plurality of semiconductor fins;

removing the fin liner from a subset of semiconductor fins of the plurality of semiconductor fins;

depositing an organic gap fill material layer on the plurality of semiconductor fins;

performing a partial recess of the organic gap fill material layer to expose an upper portion of the plurality of semiconductor fins;

removing the subset of semiconductor fins; and

removing the organic gap fill material layer.

10. The method of claim 9, wherein depositing a fin liner comprises depositing an enhanced high aspect ratio process (eHARP) oxide.

11. The method of claim 9, wherein depositing a fin liner comprises depositing silicon oxide via atomic layer deposition.

12. The method of claim 9, wherein removing the subset of semiconductor fins is performed with an anisotropic etch process.

13. The method of claim 12, wherein the removing the subset of semiconductor fins is performed with a reactive ion etch process.

14. A method of fabricating a semiconductor structure, comprising:

forming a plurality of semiconductor fins disposed on a semiconductor substrate;

depositing a fin liner on the plurality of semiconductor fins;

removing the fin liner from a subset of semiconductor fins of the plurality of semiconductor fins; and

removing the subset of semiconductor fins.

15. The method of claim 14, wherein depositing a fin liner comprises depositing an enhanced high aspect ratio process (eHARP) oxide.

16. The method of claim 14, wherein depositing a fin liner comprises depositing silicon oxide via atomic layer deposition.

17. The method of claim 14, wherein removing the subset of semiconductor fins is performed with an isotropic etch process.

18. The method of claim 17, wherein removing the subset of semiconductor fins is performed with a wet etch.

19. The method of claim 17, wherein the isotropic etch process is performed using hydrofluoric acid.

20. The method of claim 17, wherein the isotropic etch process is performed using tetramethylammonium hydroxide.