FinFET design and method of fabricating same

• US 8,618,556 B2
• Filed: 06/30/2011
• Issued: 12/31/2013
• Est. Priority Date: 06/30/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Cheng-Hsien, Ko, Chih-Hsin, Huang, Yao-Tsung, Wann, Clement Hsingjen
• Primary Examiner(s): MOORE, WHITNEY
• Application Number:
  US13/174,170
• Publication Number:
  US 20130001591A1
• Time in Patent Office: 915 Days
• Field of Search: 257/77, 257/76, 257/192, 257/E29.255, 257/E29.081, 257/E29.1, 257/E29.104, 257/E21.409, 438/197
• US Class Current: 257/77
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

An integrated circuit device and method for manufacturing the same are disclosed. An exemplary device includes a semiconductor substrate having a substrate surface and a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device. The device further includes a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge; a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant smaller than that of Ge; and a gate structure disposed over and arranged perpendicular to the first and second fin structures.

Claims

1. A device comprising:

a semiconductor substrate;

a first fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge;

a second fin structure comprising silicon or SiGe disposed over a layer of III-V semiconductor material, SiGe, or SiC having a high band gap energy and a lattice constant equal to or smaller than that of Ge; and

a gate disposed over and arranged perpendicular to the first and second fin structures.

2. The device of claim 1 further comprising a shallow trench isolation (“

STI”

) structure disposed between the fins to define an NMOS region and a PMOS region.

3. The device of claim 1 wherein the first fin is disposed in an NMOS region and the III-V semiconductor material comprising the first fin structure comprises at least one of indium phosphide (“

InP”

), aluminum indium arsenide (“

AlInAs”

), indium gallium phosphide (“

InGaP”

), indium gallium arsenide (“

InGaAs”

), gallium arsenide antimonide (“

GaAsSb”

).

4. The device of claim 1 wherein the second fin is disposed in a PMOS region and the second fin structure comprises at least one of gallium phosphide nitride (“

GaPN”

), or aluminum phosphide nitride (“

AlPN”

).

5. The device of claim 1 further comprising first source/drain (“

S/D”

) regions disposed at opposite ends of the first fin and second S/D regions disposed at opposite ends of the second fin.

6. The device of claim 5 wherein the first S/D regions are disposed in an NMOS region and comprise a III-V semiconductor material having a relatively small lattice constant.

7. The device of claim 5 wherein the second S/D regions are disposed in a PMOS region and comprise a III-V semiconductor material having a relatively large lattice constant.

8. The device of claim 7 wherein the III-V semiconductor material comprises at least one of InAs and InP.

9. A device comprising:

a semiconductor substrate having a substrate surface;

a trench isolation structure disposed in the semiconductor substrate for isolating an NMOS region of the device and from a PMOS region of the device;

a first fin structure disposed in the NMOS region and comprising silicon or SiGe disposed over a layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge;

a second fin structure disposed in the PMOS region and comprising silicon or SiGe disposed over a layer of III-V semiconductor material, SiGe, or SiC having a high band gap energy and a lattice constant equal to or smaller than that of Ge; and

a gate structure disposed over and arranged perpendicular to the first and second fin structures.

10. The device of claim 9 wherein the III-V semiconductor material comprising the first fin structure comprises at least one of indium phosphide (“

InP”

), aluminum indium arsenide (“

AlInAs”

), indium gallium phosphide (“

InGaP”

), indium gallium arsenide (“

InGaAs”

), gallium arsenide antimonide (“

GaAsSb”

).

11. The device of claim 9 wherein the second fin structure comprises at least one of gallium phosphide nitride (“

GaPN”

), or aluminum phosphide nitride (“

AlPN”

).

12. The device of claim 9 further comprising first source/drain (“

S/D”

) regions disposed at opposite ends of the first fin and second S/D regions disposed at opposite ends of the second fin.

13. A device comprising:

a silicon substrate including an NMOS region and a PMOS region;

a first fin structure in the NMOS region and comprising a first layer of silicon extending from the silicon substrate, a second layer of III-V semiconductor material having a high band gap energy and a lattice constant greater than that of Ge, and a third layer of semiconductor material;

a second fin structure in the PMOS region and comprising a first layer of silicon extending from the silicon substrate, a second layer of semiconductor material having a high band gap energy and a lattice constant less than that of Ge, and a third layer of semiconductor material; and

a gate disposed over and arranged perpendicular to the first and second fin structures.

14. The device of claim 13 further comprising a shallow trench isolation (“

STI”

) structure disposed between the NMOS region and the PMOS region.

15. The device of claim 13 wherein the second layer of III-V material in the first fin comprises at least one of InP, AlInAs, InGaP, indium gallium arsenide (“

InGaAs”

), or GaAsSb.

16. The device of claim 13 wherein the second layer of semiconductor material in the second fin comprises at least one of GaPN, AlPN, SiGe, or SiC.

17. The device of claim 13 wherein the third layer of semiconductor material in the first fin comprises at least one of Si, Ge, or SiGe.

18. The device of claim 13 wherein the third layer of semiconductor material in the second fin comprises at least one of Si, Ge, or SiGe.