Memory device, semiconductor device, and electronic device

• US 8,618,586 B2
• Filed: 01/18/2013
• Issued: 12/31/2013
• Est. Priority Date: 12/25/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US13/744,860
• Publication Number:
  US 20130127497A1
• Time in Patent Office: 347 Days
• Field of Search: 257/277, 257/298, 257/300, 257/368, 257/E27.001, 257/E27.081, 257/E27.009, 257/E27.014, 438/238, 438/241, 438/258, 438/266
• US Class Current: 257/277
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Claims

1. A semiconductor device comprising:

a first logic element;

a second logic element;

a third logic element;

a first transistor comprising a first terminal, a second terminal, and a gate;

a second transistor comprising a first terminal, a second terminal, and a gate;

a third transistor comprising a first terminal, a second terminal, and a gate;

a fourth transistor comprising a first terminal, a second terminal, and a gate;

a fifth transistor comprising a first terminal, a second terminal, and a gate; and

a capacitor,

wherein;

an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,

an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,

an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,

the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,

the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,

an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,

the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor, and

a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In and Zn.

2. The semiconductor device according to claim 1, wherein each of the first to third logic elements is any of an inverter and a clocked inverter.

3. The semiconductor device according to claim 1, wherein an off-state current of the fourth transistor is lower than or equal to 100 zA/μ

m.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor further comprises Ga.

5. A semiconductor device which is an LSI comprising a CPU, a DSP, or a microcontroller comprising the semiconductor device according to claim 1.

6. An electronic device comprising a CPU comprising the semiconductor device according to claim 1, wherein the electronic device is one selected from the group consisting of a game machine, an image reproducing device, and a personal computer.

7. A semiconductor device comprising:

a first logic element;

a second logic element;

a third logic element;

a first transistor comprising a first terminal, a second terminal, and a gate;

a second transistor comprising a first terminal, a second terminal, and a gate;

a third transistor comprising a first terminal, a second terminal, and a gate;

a fourth transistor comprising a first terminal, a second terminal, and a gate;

a fifth transistor comprising a first terminal, a second terminal, and a gate; and

a capacitor,

wherein;

an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,

an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,

an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,

the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,

the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,

an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,

the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor, and

a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In and Zn, and

a hydrogen concentration in the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

8. The semiconductor device according to claim 7, wherein each of the first to third logic elements is any of an inverter and a clocked inverter.

9. The semiconductor device according to claim 7, wherein an off-state current of the fourth transistor is lower than or equal to 100 zA/μ

m.

10. The semiconductor device according to claim 7, wherein the oxide semiconductor further comprises Ga.

11. A semiconductor device which is an LSI comprising a CPU, a DSP, or a microcontroller comprising the semiconductor device according to claim 7.

12. An electronic device comprising a CPU comprising the semiconductor device according to claim 7, wherein the electronic device is one selected from the group consisting of a game machine, an image reproducing device, and a personal computer.

13. A semiconductor device comprising:

a first logic element;

a second logic element;

a third logic element;

a first transistor comprising a first terminal, a second terminal, and a gate;

a second transistor comprising a first terminal, a second terminal, and a gate;

a third transistor comprising a first terminal, a second terminal, and a gate;

a fourth transistor comprising a first terminal, a second terminal, and a gate;

a fifth transistor comprising a first terminal, a second terminal, and a gate; and

a capacitor,

wherein;

an input terminal of the first logic element is electrically connected to the second terminal of the first transistor and the first terminal of the second transistor,

an output terminal of the first logic element is electrically connected to an input terminal of the second logic element and the first terminal of the third transistor,

an output terminal of the second logic element is electrically connected to the second terminal of the second transistor,

the second terminal of the third transistor is electrically connected to the first terminal of the fifth transistor,

the second terminal of the fifth transistor is electrically connected to an output terminal of the third logic element,

an input terminal of the third logic element is electrically connected to the second terminal of the fourth transistor and the capacitor,

the first terminal of the fourth transistor is electrically connected to the first terminal of the first transistor,

a channel formation region of the fourth transistor comprises an oxide semiconductor comprising at least In Zn, and

the channel formation region of the fourth transistor further comprises crystals which are c-axis-oriented in a direction generally perpendicular to a surface of the oxide semiconductor.

14. The semiconductor device according to claim 13, wherein each of the first to third logic elements is any of an inverter and a clocked inverter.

15. The semiconductor device according to claim 13, wherein an off-state current of the fourth transistor is lower than or equal to 100 zA/μ

m.

16. The semiconductor device according to claim 13, wherein the oxide semiconductor further comprises Ga.

17. A semiconductor device which is an LSI comprising a CPU, a DSP, or a microcontroller comprising the semiconductor device according to claim 13.

18. An electronic device comprising a CPU comprising the semiconductor device according to claim 13, wherein the electronic device is one selected from the group consisting of a game machine, an image reproducing device, and a personal computer.