Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure

• US 8,618,588 B2
• Filed: 10/29/2010
• Issued: 12/31/2013
• Est. Priority Date: 10/29/2010
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ackerson, Kristin M., Gambino, Jeffrey P., Jaffe, Mark D., Leidy, Robert K., Rassel, Richard J., Rassel, Robert M.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US12/915,888
• Publication Number:
  US 20120105692A1
• Time in Patent Office: 1,159 Days
• Field of Search: 257/292, 257/E31.127, 348/296, 716/103
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H04N 23/75 by influencing optical camera components
• CPC Class Codes: H04N 25/621 for the control of blooming

Abstract

A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Claims

1. A method of preventing blooming in a pixel array, comprising:

affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element, wherein the adjusting the transmissivity of the electrochromic element comprises turning the electrochromic element opaque prior to the photoelectric conversion element becoming saturated.

2. The method of claim 1, wherein the adjusting the transmissivity comprises creating an electric potential across an electrochromic material between first and second electrically conductive elements.

3. The method of claim 2, wherein the creating the electric potential comprises:

holding the first electrically conductive element at a reference voltage; and

changing a voltage of the second electrically conductive element away from the reference voltage based on the output of the photoelectric conversion element.

4. The method of claim 3, wherein the changing the voltage of the second electrically conductive element comprises setting the voltage of the second electrically conductive element to a voltage of a source of a source follower transistor.

5. The method of claim 4, further comprising:

coupling a gate of the source follower transistor to the output of the photoelectric conversion element; and

coupling a drain of the source follower transistor to the reference voltage.

6. The method of claim 1, further comprising affecting an amount of light that impinges on a second photoelectric conversion element by adjusting a transmissivity of a second electrochromic element based on an output of the second photoelectric conversion element, wherein the photoelectric conversion element and the second photoelectric conversion element are comprised in the pixel array in an image sensor.

7. A pixel sensor cell, comprising:

a photoelectric conversion element;

an electrochromic element arranged in a path that light travels to the photoelectric conversion element; and

a feedback circuit that is structured to adjust a transmissivity of the electrochromic element based on an output of the photoelectric conversion element,

wherein the electrochromic element comprises an electrochromic material contacting a first electrically conductive element and a second electrically conductive element;

the first electrically conductive element is electrically coupled to a reference voltage; and

the second electrically conductive element is electrically coupled to a source voltage of a source follower transistor.

8. The pixel sensor cell of claim 7, wherein:

a gate of the source follower transistor is electrically coupled to an output of the photoelectric conversion element; and

a drain of the source follower transistor is electrically coupled to the reference voltage.

9. The pixel sensor cell of claim 7, wherein the photoelectric conversion element comprises a pinned photodiode.

10. The pixel sensor cell of claim 7, wherein the feedback circuit is structured to adjust the transmissivity of the electrochromic element in a manner proportional to the output of the photoelectric conversion element.

11. The pixel sensor cell of claim 7, wherein the feedback circuit is structured to adjust the transmissivity of the electrochromic element in a binary manner between first and second states based upon a predefined threshold.

12. The pixel sensor cell of claim 7, further comprising:

a second pixel sensor cell comprising a second photoelectric conversion element;

a second electrochromic element arranged in a path that light travels to the second photoelectric conversion element; and

a second feedback circuit that adjusts a transmissivity of the second electrochromic element based on an output of the second photoelectric conversion element.

13. The pixel sensor cell of claim 12, wherein the pixel sensor cell and the second pixel sensor cell are comprised in an array in an image sensor.

14. The pixel sensor cell of claim 7, further comprising logic between the source voltage of the source follower transistor and the second electrically conductive element of the electrochromic element, wherein the logic is configured to control the electrochromic element in a binary manner by preventing the source voltage of the source follower transistor from reaching the second electrically conductive element until a threshold is achieved.

15. The pixel sensor cell of claim 7, further comprising logic that is configured to:

store an integration time to trigger the electrochromic element;

calculate a relative lux for a pixel region; and

extrapolate an image based on the calculated relative lux.

16. The pixel sensor cell of claim 7, further comprising:

the source follower transistor;

a reset gate transistor; and

a row select transistor;

wherein;

the photoelectric conversion element comprises a photodiode;

one end of the photodiode is grounded;

another end of the photodiode is connected to a floating diffusion node;

a source of the reset gate transistor is connected to the floating diffusion node;

a drain of the reset gate transistor is connected to the reference voltage;

a gate of the source follower transistor is connected to the floating diffusion node;

a drain of the source follower transistor is connected to the reference voltage;

a source of the source follower transistor is connected to a drain of the row select transistor; and

a source of the row select transistor is connected to an output node of the pixel sensor cell.

17. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a pixel sensor cell, wherein said pixel sensor cell comprises:

a photoelectric conversion element;

an electrochromic element arranged in a path that light travels to the photoelectric conversion element; and

a feedback circuit that adjusts a transmissivity of the electrochromic element based on an output of the photoelectric conversion element,

wherein the electrochromic element comprises an electrochromic material contacting a first electrically conductive element and a second electrically conductive element;

the first electrically conductive element is electrically coupled to a reference voltage; and

the second electrically conductive element is electrically coupled to a source voltage of a source follower transistor.

18. The design structure of claim 17, wherein the design structure comprises a netlist.

19. The design structure of claim 17, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

20. The design structure of claim 17, wherein the design structure resides in a programmable gate array.