Integrated circuit including a buried wiring line

• US 8,618,600 B2
• Filed: 06/09/2008
• Issued: 12/31/2013
• Est. Priority Date: 06/09/2008
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Slesazeck, Stafan
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US12/135,318
• Publication Number:
  US 20090302392A1
• Time in Patent Office: 2,031 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/E29.13, 257/E29.201, 257/E29.621, 257/E29.624
• US Class Current: 257/330
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Integrated circuits including a buried wiring lien. One embodiment provides a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate. A gate wiring line may be buried below the main surface and a section of the gate wiring line may form the gate electrode. Above the gate wiring line, a buried contact structure is formed that is adjacent to and in direct contact with the first or a second active area.

Claims

1. An integrated circuit comprising:

a field effect transistor including a first active area and a gate electrode buried below a main surface of a semiconductor substrate;

a gate wiring line buried below the main surface, wherein a section of the gate wiring line forms the gate electrode;

a buried contact element in direct contact with the gate wiring line, wherein a top of the buried contact element is substantially flush with or recessed below the main surface; and

a second active area formed in the semiconductor substrate adjacent to and in direct contact with the buried contact element;

wherein the gate electrode is buried between a first and a second source/drain region of the field effect transistor that are formed within the first active area and adjacent to the main surface;

wherein the second active area comprises a further first and a further second source/drain region of a second field effect transistor; and

wherein the buried contact element is formed adjacent to and in direct contact with one of the further first or second source/drain regions.

2. The integrated circuit of claim 1, wherein the further first and second source/drain regions adjoin to the main surface, and

the second field effect transistor comprises a second gate electrode buried below the main surface and between the further first and second source/drain regions.

3. The integrated circuit of claim 1, further comprising

a third field effect transistor including an active area adjacent to and in direct contact with the buried contact element.

4. The integrated circuit of claim 3, wherein the third field effect transistor faces the second field effect transistor at the buried contact element.

5. An integrated circuit comprising:

a plurality of field effect transistors, each of them including a gate electrode buried below a main surface of a semiconductor substrate;

an address line including and connecting the gate electrodes and completely buried below the main surface;

a buried contact element adjacent to and in direct contact with the address line and buried below the main surface; and

a driver circuit configured to drive the address line and comprising a combined active area that is adjacent to and in direct contact with the buried contact element.

6. The integrated circuit of claim 5, wherein the driver circuit comprises:

an n-FET including a first active area and a p-FET including a second active area, wherein the first and the second active areas are formed within the combined active area and are adjacent to and in direct contact with the buried contact element.

7. The integrated circuit of claim 6, wherein the n-FET comprises a first further gate electrode and the p-FET comprises a second further gate electrode, wherein the first and second further gate electrodes are buried below the main surface.

8. The integrated circuit of claim 6, wherein the n-FET and the p-FET face each other at opposing sides of the buried contact element.

9. The integrated circuit of claim 8, wherein a groove structure, in which the address line is buried, is disposed between the first and the second active areas and has a lower edge with a greater distance to the main surface than a lower edge of source/drain regions of the n-FET and the p-FET that are formed in the first and second active areas adjacent to the groove structure.

10. An integrated circuit comprising an inverter circuit comprising:

an n-FET;

a p-FET, wherein a first source/drain region of the p-FET is in low resistance contact with a second source/drain region of the n-FET and wherein the first source/drain region of the p-FET and the second source/drain region of the n-FET adjoin to a main surface of a semiconductor substrate; and

a buried contact element formed in a groove and buried below the main surface, the buried contact element being arranged between and being in direct contact with the first source/drain region of the p-FET and the second source/drain region of the n-FET,

wherein a lower edge of the groove has a greater distance to the main surface than a lower edge of the first source/drain region of the p-FET and the second source/drain region of the n-FET.

11. The integrated circuit of claim 10, further comprising:

a buried output line, a section of which is buried below and in direct contact with the buried contact element.

12. The integrated circuit of claim 11, wherein a first gate electrode configured to control the n-FET and a second gate electrode configured to control the p-FET are buried below the main surface.

13. The integrated circuit of claim 12, wherein an upper edge of at least one of the first and second gate electrodes is approximately flush with an upper edge of the buried output line.

14. An integrated circuit comprising a ring oscillator circuit including a plurality of inverter circuits, wherein individual ones of the inverter circuits comprise:

a buried contact element, at least a section of which is formed below a main surface of a semiconductor substrate and adjoins a first source/drain region of a p-FET that includes a first gate electrode and a second source/drain region of an n-FET that includes a second gate electrode, the first and the second source/drain regions formed below and directly adjacent to the main surface; and

a buried output line, at least a section of which is buried below and in direct contact with the buried contact element,

wherein the buried output lines of individual ones of the inverter circuits are connected with the first and second gate electrodes of one of the other inverter circuits.

15. The integrated circuit of claim 14, wherein the first and the second gate electrodes are buried below the main surface.

16. The integrated circuit of claim 14, wherein an upper edge of the first and second gate electrodes is approximately flush with an upper edge of the buried output lines.

17. The integrated circuit of claim 14, further comprising:

further buried contact elements formed between an upper edge of the first and second gate electrodes of one of the other inverter circuits and the main surface.

18. An integrated circuit comprising:

a field effect transistor including a first active area of a plurality of active areas formed in a semiconductor substrate, the field effect transistor comprising a first and a second source/drain region, wherein the first and the second source/drain regions directly adjoin to a main surface of the semiconductor substrate, and a gate electrode that is buried below the main surface and between the first and the second source/drain regions; and

a conductive buried contact element in contact with the gate electrode and adjoining at least one of the plurality of active areas,

wherein the distance between the buried contact element and one of the source and drain regions is not greater than two times the distance between the source region and the drain region.

19. The integrated circuit of claim 18, wherein a distance between the source region and the buried contact element is approximately equal to a distance between the drain region and the buried contact structure.

20. The integrated circuit of claim 19, wherein the distance between the source region and the buried contact element is approximately equal to a distance between the drain region and the source region.

21. The integrated circuit of claim 18, wherein the buried contact element is disposed above and in direct contact with the gate electrode, between the first and the second source/drain regions and in direct contact with one of the first and the second source/drain regions.