On-chip ferrite bead inductor

• US 8,618,631 B2
• Filed: 02/14/2012
• Issued: 12/31/2013
• Est. Priority Date: 02/14/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jin, Jun-De, Yeh, Tzu-Jin
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Singh, Harpreet
• Application Number:
  US13/372,873
• Publication Number:
  US 20130207230A1
• Time in Patent Office: 686 Days
• Field of Search: None
• US Class Current: 257/531
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

Claims

1. A semiconductor structure with chip-level ferrite bead inductor comprising:

a substrate;

a first dielectric layer formed on the substrate;

a lower ferrite layer formed on the first dielectric layer and an upper ferrite layer spaced vertically apart from the lower ferrite layer;

a first metal layer formed above the lower ferrite layer;

a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration; and

at least one second dielectric layer disposed between the first and second metal layers.

2. The semiconductor structure of claim 1, further comprising a conductive via electrically connecting the first and second metal layers together.

3. The semiconductor structure of claim 1, wherein the first metal layer is configured as a straight conductive lead.

4. The semiconductor structure of claim 1, further comprising:

a third dielectric layer disposed between the first and second metal layers; and

a third metal layer disposed between the upper and lower ferrite layer, and further disposed between the second and third dielectric layers.

5. The semiconductor structure of claim 4, wherein the first, second, and third metal layers have a coil configuration.

6. The semiconductor structure of claim 5, wherein the first, second, and third metal layers are electrically interconnected by conductive vias extending vertically through the semiconductor structure.

7. The semiconductor structure of claim 1, wherein the substrate is silicon or high resistivity silicon.

8. The semiconductor structure of claim 1, wherein the second dielectric layer has a greater thickness than the first dielectric layer.

9. The semiconductor structure of claim 1, wherein the second dielectric layer directly contacts both the first and second metal layers.

10. A semiconductor chip with in situ ferrite bead inductor comprising:

a substrate;

a first dielectric layer formed on the substrate;

a planar lower ferrite layer formed on the first dielectric layer;

a first metal layer formed on the lower ferrite layer;

a second dielectric layer formed on the first metal layer;

a second metal layer formed on the second dielectric layer, the second metal layer being patterned to define a first conductive coil comprising multiple turns;

a via electrically connecting the first conductive coil to the first metal layer; and

a planar upper ferrite layer disposed above the first conductive coil.

11. The semiconductor chip of claim 10, wherein the upper ferrite layer directly contacts the first conductive coil.

12. The semiconductor chip of claim 10, wherein the first metal layer is patterned to define a conductive straight lead.

13. The semiconductor chip of claim 10, wherein the first metal layer is patterned to define a second conductive coil comprising multiple turns.

14. The semiconductor chip of claim 10, further comprising:

a third dielectric layer disposed between the first and second metal layers; and

a third metal layer disposed between the upper and lower ferrite layer, and further disposed between the second and third dielectric layers.

15. The semiconductor chip of claim 10, wherein the substrate is silicon or high resistivity silicon.

16. The semiconductor chip of claim 15, wherein the substrate is a CMOS substrate containing active devices.

17. The semiconductor chip of claim 10, wherein the second dielectric layer directly contacts both the first and second metal layers.

18. A method for forming an in situ chip-level ferrite bead inductor comprising:

depositing a first dielectric layer on a substrate;

depositing a lower ferrite layer on the first dielectric layer;

depositing a first metal layer on the lower ferrite layer;

patterning the first metal layer to form a first conductive lead having a configuration;

depositing a second dielectric layer on the patterned first metal layer;

depositing a second metal layer on the second dielectric layer;

patterning the second metal layer to form a conductive coil having multiple turns; and

forming an upper ferrite layer above the patterned second metal layer.

19. The method of claim 18, wherein the upper ferrite layer is formed directly onto the patterned second metal layer.

20. The method of claim 18, further comprising:

depositing a third dielectric layer on the patterned second metal layer;

depositing a third metal layer on the third dielectric layer; and

patterning the third metal layer to form a conductive coil having multiple turns.