Switch-mode regulator including hysteretic control

• US 8,618,779 B2
• Filed: 11/15/2010
• Issued: 12/31/2013
• Est. Priority Date: 11/24/2009
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Garrett, James, Bridge, Christopher D.
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US12/946,458
• Publication Number:
  US 20110121806A1
• Time in Patent Office: 1,142 Days
• Field of Search: 323/222, 323/271, 323/283, 323/284, 323/285, 323/299
• US Class Current: 323/271
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

This document discusses, among other things, a regulator circuit. The regulator circuit can controllably connect a first voltage to an inductor using a first switch and can controllably connect a second voltage to the inductor using a second switch. The first switch can be turned off and the second switch can be turned on for a duration proportional to a difference between the first voltage and a third voltage, divided by the first voltage. The first switch can be turned off and the second switch can be turned on for a duration proportional to the third voltage divided by the first voltage. One of the first or third voltages can correspond to a desired output voltage.

Claims

1. A regulator circuit, comprising:

a first switch configured to controllably connect a first voltage to an inductor;

a second switch configured to controllably connect a second voltage to the inductor;

a switch control circuit configured to control the first and second switches using a timer circuit;

wherein the switch control circuit is configured to turn off the first switch and to turn on the second switch for a duration proportional to a difference between the first voltage and a third voltage, divided by the first voltage;

wherein the switch control circuit is configured to turn on the first switch and to turn off the second switch for a duration proportional to the third voltage divided by the first voltage;

wherein one of the first or third voltages corresponds to a desired output voltage;

wherein the second voltage is less than the first and third voltages; and

wherein the switch control circuit includes at least one of a peak threshold control circuit and a valley threshold control circuit and wherein the switch cycling period is adjustable using the at least one of the peak threshold control circuit and the valley threshold control circuit.

2. The regulator circuit of claim 1, wherein the timer circuit includes a digital timer circuit.

3. The regulator circuit of claim 1, wherein the first voltage comprises an input voltage supplied to the regulator circuit;

wherein the third voltage comprises a desired output voltage; and

wherein the first voltage is greater than the third voltage.

4. The regulator circuit of claim 1, wherein the third voltage comprises an input voltage supplied to the regulator circuit;

wherein the first voltage comprises a desired output voltage; and

wherein the first voltage is greater than the third voltage.

5. The regulator circuit of claim 1, wherein the total on-time of the first and second switches corresponds to a specified period when the regulator is driving a specified load;

and

wherein the specified period corresponds to a desired steady-state operating frequency.

6. The regulator circuit of claim 1, wherein the timer circuit comprises:

a first ramp generator configured to generate a first ramp signal coupled to a first comparator;

a second ramp generator configured to generate a second ramp signal coupled to a second comparator; and

wherein the switch control circuit is configured to control the first and second switches using the first and second comparators and the first and second ramp generators.

7. The regulator circuit of claim 6, wherein the respective first and second ramp generators include respective first and second capacitors, and wherein each of the respective first and second capacitors are charged by respective first and second current sources.

8. The regulator circuit of claim 7, wherein the first and second current sources are configured to drive respective specified first and second currents proportional to the voltage at the voltage input;

and

wherein the first and second current sources are configured to control respective first and second slew rates of the respective first and second ramp signals.

9. The regulator circuit of claim 6, wherein the switch control circuit comprises:

a set-reset (SR) latch;

wherein the first comparator output is coupled to a reset input of the SR latch;

wherein the second comparator output is coupled to a set input of the SR latch;

wherein a non-inverted output of the SR latch is coupled to the first switch;

wherein an inverted output of the SR latch is coupled to the second switch;

wherein the SR latch is configured to turn on or off the respective first and second switches in a mutually-exclusive manner; and

wherein the total on-time of the first and second switches corresponds to a specified period when the regulator is driving a specified load.

10. The regulator circuit of claim 6, wherein the first ramp signal increases with time;

and

wherein the first comparator is configured to compare the first ramp signal with a specified peak threshold, and in response, wherein the switch control logic is configured to turn on the second switch, and to reset the first ramp signal to a voltage at the inductor at a node opposite the first and second switches, when the first ramp signal reaches the specified peak threshold.

11. The regulator circuit of claim 10, wherein the specified peak threshold is proportional to and greater than the third voltage.

12. The regulator circuit of claim 1, wherein the timer circuit comprises:

a first ramp generator configured to generate a first ramp signal coupled to a first comparator;

a second ramp generator configured to generate a second ramp signal coupled to a second comparator; and

wherein the second ramp signal decreases with time; and

wherein the second comparator is configured to compare the second ramp signal with a specified valley threshold, and in response, wherein the switch control logic is configured to turn on the first switch, and to reset the second ramp signal to a voltage at the inductor at a node opposite the first and second switches, when the second ramp signal reaches the specified valley threshold.

13. The regulator circuit of claim 12, wherein the specified valley threshold is proportional to and less than the third voltage.

14. The regulator circuit of claim 12, wherein the specified valley threshold is controlled by a valley threshold control circuit;

and

wherein the valley threshold control circuit is configured to provide a valley threshold less than the third voltage by a voltage proportional to the difference between the first voltage and the third voltage.

15. The regulator circuit of claim 14, wherein the valley threshold control circuit includes an adjustable gain;

and

wherein the specified valley threshold is scaled by the adjustable gain.

16. The regulator circuit of claim 15, wherein the adjustable gain is controlled using information about a difference between the first voltage and the third voltage.

17. A method, comprising:

controllably connecting a first voltage to an inductor using a first switch;

controllably connecting a second voltage to the inductor using a second switch;

turning off the first switch and turning on the second switch for a duration proportional to a difference between the first voltage and a third voltage, divided by the first voltage; and

turning on the first switch and turning off the second switch for a duration proportional to the third voltage divided by the first voltage, wherein one of the first or third voltages corresponds to a desired output voltage, and wherein the second voltage is less than the first and third voltages; and

adjusting a switch cycling period using at least one of a peak threshold control circuit and a valley threshold control circuit.

18. The method of claim 17, comprising providing a desired output voltage corresponding to the third voltage using the controllably connecting the first voltage and the controllably connecting the second voltage, wherein the first voltage comprises an input voltage greater than the third voltage.

19. The method of claim 17, comprising providing a desired output voltage corresponding to the first voltage using the controllably connecting the first voltage and the controllably connecting the second voltage, wherein the third voltage comprises an input voltage, and wherein the first voltage is greater than the third voltage.

20. The method of claim 17, comprising controlling the total on-time of the first and second switches corresponding to a specified period when the inductor is driving a specified load, wherein the specified period corresponds to a desired steady-state operating frequency.