Methods and apparatus of stacking DRAMs

• US 8,619,452 B2
• Filed: 09/01/2006
• Issued: 12/31/2013
• Est. Priority Date: 09/02/2005
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh N., Smith, Michael J. S., Wang, David T
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US11/515,223
• Publication Number:
  US 20070058471A1
• Time in Patent Office: 2,678 Days
• Field of Search: 365/51, 365/52, 365/63, 365/222, 365/233.1, 365/230.03, 711/105, 711/167, 711/170
• US Class Current: 365/51
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.

Claims

1. A memory device comprising:

a plurality of dynamic random access memory (“

DRAM”

) integrated circuits stacked in a vertical direction; and

a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits,

wherein the buffer integrated circuit is configured to track addresses of “

m”

previous reads and compare an address of a current read with the tracked addresses of the “

m”

previous reads.

2. The memory device as set forth in claim 1, wherein the buffer integrated circuit is configured to provide an interface for a plurality of stacks of the DRAM integrated circuits.

3. The memory device as set forth in claim 1, wherein said stacked DRAM integrated circuits comprise p+q DRAM integrated circuits, wherein “

p”

DRAM integrated circuits comprise a number of DRAM integrated circuits used as a working pool of memory integrated circuits, and wherein “

q”

DRAM integrated circuits comprise a number of DRAM integrated circuits used as a spare pool of memory integrated circuits, wherein “

p” and

“

q”

comprise integer values.

4. The memory device as set forth in claim 3, wherein the buffer integrated circuit is configured to replace at least one DRAM integrated circuit from the working pool of memory integrated circuits with at least one DRAM integrated circuit from the spare pool of memory integrated circuits.

5. The memory device as set forth in claim 3, wherein the buffer integrated circuit is configured to determine whether a pre-defined number of errors occurred in the working memory integrated circuits and configured to replace at least one DRAM integrated circuit from the working pool of memory integrated circuits with at least one DRAM integrated circuit from the spare pool of memory integrated circuits.

6. The memory device as set forth in claim 1, further comprising a socket, coupled to the stack, and configured to accommodate adding at least one additional DRAM integrated circuit to said stack.

7. The memory device of claim 1 wherein the buffer integrated circuit is configured to perform conversion between signal timing such that a signal of the second protocol is asserted for a duration that is different from a duration of the corresponding signal of the first protocol,

wherein the signal of the second protocol is selected from the group consisting of address signal, control signal, and data signal.

8. The memory device of claim 1, wherein the buffer integrated circuit is further configured to perform conversion between signal types of the first protocol and the second protocol.

9. The memory device of claim 1, wherein, the buffer chip is configured such that, if the buffer chip detects a match between the address of the current read and one of the addresses of the “

m”

previous reads, the buffer chip reads contents of a memory location from a mirrored memory set instead of a working memory set.

10. A method for controlling a memory device comprising a plurality of dynamic random access memory (“

DRAM”

) integrated circuits, the method comprising;

providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus; and

performing conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits;

tracking addresses of “

m”

previous reads; and

comparing the address of a current read with the tracked addresses of the “

m”

previous reads.

11. The method of claim 10 wherein performing conversion between signal timing further includes asserting a signal of the second protocol for a duration that is different from a duration of a corresponding signal of the first protocol,

wherein the signal of the second protocol is selected from the group consisting of address signal, control signal, and data signal.

12. The method of claim 10 further comprising performing conversion between signal types of the first protocol and the second protocol.

13. The method of claim 10 further comprising performing conversion between a number of signals of the first protocol and a number of signals of the second protocol.

14. The method of claim 10 further comprising:

reading contents of a memory location from a mirrored memory set in response to detecting a match between the address of the current read and one of the addresses of the “

m”

previous reads.

15. A memory device comprising:

a plurality of dynamic random access memory (“

DRAM”

) integrated circuits stacked in a vertical direction; and

a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits,

wherein the buffer integrated circuit is configured to track errors and to execute a read operation to a mirrored memory set based on one or more of the tracked errors.

16. The memory device as set forth in claim 15 wherein the buffer integrated circuit is configured to keep track of a number of the errors that occur over a period of time and, if the number of errors that occur over the period of time exceeds a threshold, the buffer integrated circuit switches from a working memory set to the mirrored memory set.

17. The memory device as set forth in claim 16 wherein the buffer integrated circuit is configured such that, upon switching from the working memory set to the mirrored memory set, the buffer integrated circuit notifies an external device that the working memory set is being disabled.

18. The memory device as set forth in claim 16 wherein keeping track of the number of errors includes keeping track of a number of second reads from a memory controller to a memory location in the working memory set due to uncorrectable error.

19. A memory device comprising:

a plurality of dynamic random access memory (“

DRAM”

) integrated circuits stacked in a vertical direction; and

a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits,

wherein said stacked DRAM integrated circuits comprise p+q DRAM integrated circuits, wherein “

p”

DRAM integrated circuits comprise a number of DRAM integrated circuits used as a working pool of memory integrated circuits, and wherein “

q”

DRAM integrated circuits comprise a number of DRAM integrated circuits used as a mirrored pool of memory integrated circuits, wherein “

p” and

“

q”

comprise integer values,

wherein the buffer integrated circuit is configured to track addresses of “

m”

previous reads, compare an address of a current read with the tracked addresses of the “

m”

previous reads, and if the buffer integrated circuit detects a match between the address of the current read and one or more of the tracked addresses of the “

m”

previous reads, read contents from a memory location in the mirrored pool that corresponds to the address of the current read.

20. The memory device as set forth in claim 19, wherein the buffer integrated circuit is configured to keep track of how many times the buffer integrated circuit detects a match between the address of the current read and one or more of the tracked addresses of the “

m”

previous reads over a period of time.

21. The memory device as set forth in claim 20, wherein the buffer integrated circuit is configured such that, if the number of times that the buffer detects a match exceeds a threshold within a time window, then the buffer chip permanently switches to the mirrored pool of memory integrated circuits.

22. The memory device as set forth in claim 21, wherein the buffer integrated circuit is configured, such that when the buffer integrated chip permanently switches to the mirrored pool of memory integrated circuits, the buffer integrated circuit notifies an external device that the working set has been disabled.