Adaptive write bit line and word line adjusting mechanism for memory

• US 8,619,463 B2
• Filed: 11/14/2012
• Issued: 12/31/2013
• Est. Priority Date: 08/03/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Cheng, Hank, Kuo, Ming-Zhang, Chou, Chung-Cheng
• Primary Examiner(s): Phan, Trong
• Application Number:
  US13/676,389
• Publication Number:
  US 20130070550A1
• Time in Patent Office: 412 Days
• Field of Search: 365/149, 365/189.09, 365/203, 365/226, 365/230.06
• US Class Current: 365/149
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory including a capacitor coupled to a write bit line or a word line and an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line. The memory further includes a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse. The capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node. The boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

Claims

1. A memory, comprising:

a capacitor coupled to a write bit line or a word line;

an initializer configured to initialize a voltage level at a first node between the capacitor and the write bit line or the word line;

a controllable initial level adjuster configured to adjust a voltage level of a second node at one terminal of the capacitor in response to a pulse;

wherein the capacitor is configured to receive a boost signal at a third node at a terminal opposite the first node, the boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

2. The memory of claim 1, wherein the controllable initial level adjuster is configured to adjust the voltage level at the second node based on a voltage level of a supply voltage.

3. The memory of claim 1, wherein the first node and the second node are the same.

4. The memory of claim 1, further comprising a transistor configured to couple the capacitor to the write bit line or the word line.

5. The memory of claim 1, wherein the capacitor is coupled to the write bit line and the initializer is configured to initialize the voltage level at the first node to a supply voltage.

6. The memory of claim 1, wherein the capacitor is coupled to the word line and the initializer is configured to initialize the voltage level at the first node to a ground voltage .

7. The memory of claim 1, further comprising a pulse generator configured to control the controllable initial level adjuster, the pulse generator configured to selectively activate the controllable initial level based on a voltage level of a supply voltage.

8. A boost circuit, comprising:

a capacitor coupled to a write bit line or a word line;

an initializer configured to pre-charge a first node between the capacitor and the write bit line or the word line; and

a controllable initial level adjuster configured to adjust a voltage level of the pre-charged first node in response to a pulse,

wherein the capacitor is configured to receive a boost signal at a second node at a terminal opposite the first node, the boost signal configured to change a voltage level of the write bit line or the word line in response to the boost signal.

9. The boost circuit of claim 8, further comprising an inverter positioned between the second node and the capacitor.

10. The boost circuit of claim 8, further comprising a pulse generator configured to control the controllable initial level adjuster, the pulse generator configured to selectively activate the controllable initial level based on a voltage level of a supply voltage.

11. The boost circuit of claim 8, wherein the controllable initial level adjuster is configured to raise the voltage level of the pre-charged first node.

12. The boost circuit of claim 8, wherein the controllable initial level adjuster is configured to lower the voltage level of the pre-charged first node.

13. The boost circuit of claim 8, wherein the capacitor is coupled to the write bit line and the initializer is configured to pre-charge the first node to a supply voltage.

14. The boost circuit of claim 8, wherein the capacitor is coupled to the word line and the initializer is configured to pre-charge the first node to a ground voltage.

15. A method of biasing a write bit line or a word line, the method comprising:

pre-charging a first node at a first terminal of a capacitor to a pre-charged voltage level using an initializer, wherein the capacitor is coupled to the write bit line or the word line;

adjusting a voltage level of a second node using a controllable initial level adjuster;

supplying a boost signal to a third node to a second terminal of the capacitor opposite the first terminal to bias a voltage level of the write bit line lower or bias the word line.

16. The method of claim 15, wherein adjusting the voltage level of the second node comprises adjusting the voltage level at the third node.

17. The method of claim 15, wherein adjusting the voltage level at the second node comprises adjusting the voltage level at the first node.

18. The method of claim 15, wherein adjusting the voltage level at the second node comprises adjusting the voltage level at the second node in response to a pulse signal, wherein a width of the pulse signal is based on a voltage level of a supply voltage.

19. The method of claim 15, wherein adjusting the voltage level at the second node comprises boosting the voltage level at the second node below a ground voltage, and the capacitor is coupled to the write bit line.

20. The method of claim 15, wherein adjusting the voltage level at the second node comprises boosting the voltage level at the second node above a supply voltage, and the capacitor is coupled to the word line.