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Semiconductor memory device with long data holding period

  • US 8,619,470 B2
  • Filed: 06/16/2011
  • Issued: 12/31/2013
  • Est. Priority Date: 06/23/2010
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a source line;

    a bit line; and

    first to m-th memory cells electrically connected in series between the source line and the bit line,wherein each of the first to m-th memory cells comprises;

    a first transistor including a first gate terminal, a first source terminal, and a first drain terminal;

    a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and

    a capacitor,wherein a second source terminal of a k-th (k is a natural number greater than or equal to 1 and less than or equal to m) memory cell is electrically connected to a second drain terminal of a memory cell adjacent to the k-th memory cell, or a second drain terminal of the k-th memory cell is electrically connected to a second source terminal of a memory cell adjacent to the k-th memory cell,wherein a first gate terminal of the k-th memory cell, the second source terminal of the k-th memory cell, and one of terminals of a capacitor of the k-th memory cell are electrically connected to each other and form a node of the k-th memory cell, andwherein the node of the k-th memory cell is supplied with a potential higher than a potential of the second gate terminal of the k-th memory cell in a data holding period in which the second gate terminal is supplied with a potential at which the second transistor is turned off.

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