Apparatuses and methods including memory array data line selection
First Claim
Patent Images
1. An apparatus comprising:
- data lines;
a node; and
a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node, wherein the node is coupled to reference voltage wherein the memory cell strings comprise U-shaped strings.
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Accused Products
Abstract
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.
32 Citations
46 Claims
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1. An apparatus comprising:
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data lines; a node; and a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node, wherein the node is coupled to reference voltage wherein the memory cell strings comprise U-shaped strings.
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2. An apparatus comprising:
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data lines; a node; a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node; and a substrate, wherein the selector includes a first transistor overlying the substrate and a second transistor overlying the first transistor.
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3. An apparatus comprising:
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data lines; a node; a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node; and a substrate, wherein the selector includes a first gate overlying the substrate and a second gate overlying the first gate.
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4. An apparatus comprising:
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data lines; a node; a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node; a sense circuit configured to receive a signal from the node; and a transistor, wherein the transistor includes a first node coupled to the node and a second node coupled to the sense circuit. - View Dependent Claims (5)
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6. An apparatus comprising:
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data lines; a node; and a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node, wherein the selector includes a bias unit configured to couple the data lines to different voltages in different memory operations. - View Dependent Claims (7, 8)
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9. An apparatus comprising:
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a substrate; a data line overlying the substrate; a first body region coupled to the data line and having a length in a direction between the substrate and the data line, first gates located along the length of the first body region, and a first material between the first body region and the first gates, wherein at least a portion of the first material is configured to store information; and a second body region coupled to the data line and having a length in the direction between the substrate and the data line, second gates located along the length of the second body region, and a second material between the second body region and the second gate, and no portion of the second material is configured to store information. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An apparatus comprising:
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a first device level and a second device level; a memory cell string including a first memory cell located at the first device level and a second memory cell located at the second device level; a conductive line configured to exchange information with the memory cell string; and a switching circuit configured to selectively exchange the information with a node, the circuit including a number of gates, the gates including a first gate located at the first device level and a second gate located at the second device level. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. An apparatus comprising:
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a data line including a first segment and a second segment separated from the first segment; a memory cell string coupled to the first segment, the memory cell string including a first body region having a length and first gates located along the length of the first body region; and a switching circuit having a second body region coupled to the first segment and a third body region coupled to the second segment, a conductive line coupling the second body region to the third body region, and second gates located along a length of the first and second and third body regions. - View Dependent Claims (27, 28, 29, 30)
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31. An apparatus comprising:
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a first memory cell string including a first body region, first gates located along a length of the first body region, and a first material between the first gates and the first body region, wherein at least a portion of the first material is configured to store information; a second memory cell string including a second body region, second gates located along a length of the second body region, and a second material between the gates and the second body region, wherein at least a portion of the second material is configured to store information; a first data line coupled to the first memory cell string; a second data line coupled to the second memory cell string; and a selector configured to selectively couple one of the first and second data lines to a node, the selector including a third body region, third gates located along a length of the third body region, and a third material between the third gates and the third body region, wherein the third gates are coupled together.
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32. An apparatus comprising:
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a first memory cell string including a first body region, first gates located along a length of the first body region, and a first material between the first gates and the first body region, wherein at least a portion of the first material is configured to store information; a second memory cell string including a second body region, second gates located along a length of the second body region, and a second material between the gates and the second body region, wherein at least a portion of the second material is configured to store information; a first data line coupled to the first memory cell string; a second data line coupled to the second memory cell string; a selector configured to selectively couple one of the first and second data lines to a node, the selector including a third body region, third gates located along a length of the third body region, and a third material between the third gates and the third body region; a substrate and a sense circuit formed in the substrate, wherein the selector includes at least one transistor overlying the substrate; and an additional transistor coupled between the selector and the sense circuit, wherein the additional transistor is configured to operate at a voltage higher than a supply voltage of the apparatus.
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33. An apparatus comprising:
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a substrate; a node; a sense circuit coupled to the node, the sense circuit including at least a portion formed in the substrate; data lines coupled to the node; and a memory array formed over the substrate, the memory array including first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node, wherein the memory array further includes a third portion included in the selector, the third portion includes a bias circuit configured to selectively couple the data lines to a reference voltage. - View Dependent Claims (34)
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35. A method comprising:
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applying a same voltage to all gates of a circuit of an apparatus in a first operation of the apparatus, the circuit coupled between a first segment of a data line and a second segment of the data line of the apparatus, the first segment coupled to a memory cell string, the memory cell string including a first memory cell located at a first device level of the device and a second memory cell located at a second device level of the apparatus; and applying the same voltage to each of the gates of the circuit in a second operation of the apparatus. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification