Semiconductor memory device and method of controlling the same

• US 8,619,487 B2
• Filed: 01/23/2012
• Issued: 12/31/2013
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Nishimura, Koichi, Fujioka, Shinya, Kawakubo, Tomohiro, Sato, Kotoku
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/356,341
• Publication Number:
  US 20120120739A1
• Time in Patent Office: 708 Days
• Field of Search: 365/222, 365226-229, 327/544
• US Class Current: 365/222
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Claims

1. A semiconductor device comprising:

a memory core with a plurality of memory cells;

an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and

wherein the internal voltage generator includes a detector and a booster circuit.

2. The semiconductor device according to claim 1, wherein

the detector compares the boosted internal voltage with a reference voltage and outputs a comparison signal, and the booster circuit, coupled to the detector, does pumping operation in response to the comparison signal to generate the boosted internal voltage.

3. The semiconductor device according to claim 2, further comprising:

a divider circuit that divides the boosted internal voltage to generate a divided voltage,

wherein the divided voltage is supplied to the detector.

4. The semiconductor device according to claim 1, wherein

the detector includes a circuit, coupled to the low power entry circuit, whose operation is stopped in response to the low power signal.

5. The semiconductor device according to claim 1, wherein

the booster circuit includes a plurality of booster units that are inactivated in response to the low power signal.

6. The semiconductor device according to claim 1, wherein

the external voltage is supplied to the internal power supply line in the low power consumption mode.

7. A semiconductor device comprising:

a memory core with a plurality of memory cells;

an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator includes a plurality of booster circuits coupled to the low power entry circuit, and a detector, and

wherein at least one of the plurality of booster circuits is inactivated in response to the low power signal.

8. The semiconductor device according to claim 7, wherein

the detector compares the boosted internal voltage with a reference voltage and outputs a comparison signal, and the plurality of booster circuits, coupled to the detector, do pumping operations in response to the comparison signal to generate the boosted internal voltage.

9. The semiconductor device according to claim 8, further comprising:

a divider circuit that divides the boosted internal voltage to generate a divided voltage,

wherein the divided voltage is supplied to the detector.

10. A semiconductor device comprising:

a memory core with a plurality of memory cells;

an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein a voltage, which is lower than the boosted internal voltage, is supplied to the internal power supply line in the low power consumption mode, and

wherein the internal voltage generator includes a detector and a booster circuit.

11. The semiconductor device according to claim 10, wherein

the external voltage is supplied to the internal power supply line as the voltage.

12. A semiconductor device comprising:

a memory core including a plurality of memory cells;

an internal voltage generator, coupled to the memory core via an internal power supply line, that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and

wherein the internal voltage generator includes a comparator, a divider circuit and a regulator.

13. The semiconductor device according to claim 12, wherein

the divider circuit generates a divided voltage,

the comparator compares the divided voltage with a reference voltage and supplies a comparison voltage to the regulator, and

the regulator outputs the internal voltage in response to the comparison voltage and

wherein the divider circuit divides the comparison voltage to generate the divided voltage.

14. The semiconductor device according to claim 12, wherein

the internal power supply line is disconnected from the regulator based on the low power signal.

15. The semiconductor device according to claim 12, wherein

the external voltage is supplied to the internal power supply line in the low power consumption mode.

16. A semiconductor device provided on a substrate comprising:

an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to the substrate via an internal power supply line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and

wherein the internal voltage generator includes an oscillator and a pumping circuit.

17. The semiconductor device according to claim 16, further comprising:

a detector that detects a level of the internal voltage and outputs a detected signal; and

wherein the oscillator, coupled to the detector, generates a clock signal in response to the detected signal, and the pumping circuit, coupled to the oscillator, does pumping operation in response to the clock signal.

18. The semiconductor device according to claim 17, wherein

the detector includes a circuit, coupled to the low power entry circuit, whose operation is stopped in response to the low power signal.

19. The semiconductor device according to claim 17, wherein

the internal voltage generator comprises at least one of a plurality of units which are inactivated in response to the low power signal.

20. The semiconductor device according to claim 16, wherein

the external voltage is supplied to the internal power supply line in the low power consumption mode.

21. A semiconductor device comprising:

a bit line coupled to a memory cell;

an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and

wherein the internal voltage generator includes a comparator.

22. The semiconductor device according to claim 21, wherein

the comparator, compares the precharge voltage with a reference voltage to output the precharge voltage.

23. The semiconductor device according to claim 21, wherein

the external voltage is supplied to the bit line in the low power consumption mode.

24. The semiconductor device according to claim 21, wherein

the comparator includes a first comparator unit and a second comparator unit,

the first comparator unit compares the precharge voltage with a first reference voltage,

the second comparator unit compares the precharge voltage with a second reference voltage, and

the first and second comparator units generate the precharge voltage supplied to the bit line.

25. A semiconductor device comprising:

a bit line coupled to a memory cell;

an internal voltage generator that generates a precharge voltage based on an external voltage and supplies the precharge voltage to the bit line; and

a low power entry circuit that receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the precharge voltage to the bit line in response to the low power signal while the external voltage is supplied to the semiconductor device, and

wherein the internal voltage generator includes a first comparator unit comparing the precharge voltage with a first reference voltage to output a first comparison signal, a second comparator unit comparing the precharge voltage with a second reference voltage to output a second comparison signal, and a driver circuit, and

wherein the driver circuit includes a first driver unit operating responsive to the first comparison signal, and a second driver unit operating responsive to the second comparison signal, and

wherein the precharge voltage is supplied from a common output node of the first and second driver units to the bit line.