Flexible memory operations in NAND flash devices
First Claim
1. A flash memory device formed on a single semiconductor chip, the flash memory device comprising:
- a memory element configured to perform memory operations, the memory element including at least two memory banks each having local core circuitry, each of the at least two memory banks having a configurable page size for receiving and providing data having different page sizes during memory operations,each of the at least two memory banks including two memory planes, each having NAND memory cell strings connected to bitlines and wordlines connected to flash memory cells of each of the NAND memory cell strings; and
core controller circuitry configured to receive control signals corresponding to the memory operations and for concurrently controlling the at least two memory banks in response to the received control signals.
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Abstract
A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.
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Citations
19 Claims
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1. A flash memory device formed on a single semiconductor chip, the flash memory device comprising:
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a memory element configured to perform memory operations, the memory element including at least two memory banks each having local core circuitry, each of the at least two memory banks having a configurable page size for receiving and providing data having different page sizes during memory operations, each of the at least two memory banks including two memory planes, each having NAND memory cell strings connected to bitlines and wordlines connected to flash memory cells of each of the NAND memory cell strings; and core controller circuitry configured to receive control signals corresponding to the memory operations and for concurrently controlling the at least two memory banks in response to the received control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification