Flexible memory operations in NAND flash devices

• US 8,619,493 B2
• Filed: 01/11/2012
• Issued: 12/31/2013
• Est. Priority Date: 02/04/2008
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/348,107
• Publication Number:
  US 20120113721A1
• Time in Patent Office: 720 Days
• Field of Search: 365/238.5, 365/230.03, 365/230.06, 365/185.11, 365/189.05, 711/170, 711/171, 711/173
• US Class Current: 365/238.5
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase operations. Each core controller controls timing and activation of row circuits, column circuits, voltage generators, and local input/output path circuits for a corresponding memory access operation of the bank. Concurrent operations are executable in multiple banks to improve performance. Each bank has a page size that is configurable with page size configuration data such that only selected wordlines are activated in response to address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank.

Claims

1. A flash memory device formed on a single semiconductor chip, the flash memory device comprising:

a memory element configured to perform memory operations, the memory element including at least two memory banks each having local core circuitry, each of the at least two memory banks having a configurable page size for receiving and providing data having different page sizes during memory operations,

each of the at least two memory banks including two memory planes, each having NAND memory cell strings connected to bitlines and wordlines connected to flash memory cells of each of the NAND memory cell strings; and

core controller circuitry configured to receive control signals corresponding to the memory operations and for concurrently controlling the at least two memory banks in response to the received control signals.

2. The flash memory device of claim 1, further including a row predecoder receiving a row address and a bank address, the row predecoder providing predecoded row addresses corresponding to a selected memory bank of the at least two memory banks in response to the bank address and the row address.

3. The flash memory device of claim 1, further including a column predecoder receiving a column address and a bank address, the column predecoder providing a predecoded column address corresponding to a selected memory bank of the at least two memory banks in response to the bank address and the row address.

4. The flash memory device of claim 1, wherein the two memory planes are each adjacent a shared row decoder.

5. The flash memory device of claim 1, wherein the flash memory cells connected to a wordline forms a page unit having a predetermined page size.

6. The flash memory device of claim 5, wherein the configurable page size includes one of a single page unit from one of the two memory planes and two page units.

7. The flash memory device of claim 5, further including page size configurators corresponding to each of the each of the at least two memory banks for selectively enabling activation of at least one wordline in each of the two memory planes in response to an address.

8. The flash memory device of claim 7, wherein each of the at least two memory banks includes one of the page size configurators.

9. The flash memory device of claim 7, wherein each of the two memory planes includes a row decoder enabled by the page size configurator for driving the at least one wordline with a global row drive signal.

10. The flash memory device of claim 7, wherein the two memory planes are each adjacent a shared row decoder enabled by the page size configurator for driving the at least one wordline with a global row drive signal.

11. The flash memory device of claim 10, wherein the shared row decoder includes a row driver for selectively passing the global row drive signal to the at least one wordline in response to first and second enable signals provided by the page size configurator.

12. The flash memory device of claim 11, wherein the row driver includes a first pass transistor for passing the global row drive signal to a first wordline in response to the first enable signal, and a second pass transistor for passing the global row drive signal to a second wordline in response to the second enable signal.

13. The flash memory device of claim 12, wherein the first enable signal and the second enable signal are driven to a high voltage level greater than a voltage level of the global row drive signal.

14. The flash memory device of claim 13, wherein the shared row decoder further includes a block decoder for providing a master voltage as the first enable signal in response to a first plane select signal, and as the second enable signal in response to a second plane select signal.

15. The flash memory device of claim 1, wherein each of the at least two memory banks includes four memory planes each having NAND memory cell strings connected to bitlines and wordlines connected to flash memory cells of each of the NAND memory cell strings.

16. The flash memory device of claim 15, further including a page size configurator corresponding to one of the at least two memory banks for selectively enabling activation of at least one wordline in each of the four memory planes of the one of the at least two memory banks, in response to an address.

17. The flash memory device of claim 16, wherein the four memory planes of the one of the at least two memory banks are arranged as a first tile and a second tile, the first tile and the second tile each having memory planes adjacent a shared row decoder.

18. The flash memory device of claim 17, wherein the page size configurator selectively enables activation of at least one wordline in each of the four memory planes in response to a tile address and a plane address.

19. The flash memory device of claim 18, wherein the flash memory cells connected to one wordline forms a page unit having a predetermined page size, and the configurable page size includes any combination of page units from each of the four memory planes.