Apparatus for receiving signal and method of compensating phase mismatch thereof

• US 8,619,916 B2
• Filed: 01/10/2011
• Issued: 12/31/2013
• Est. Priority Date: 03/11/2010
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jong, Ilyong
• Primary Examiner(s): Torres, Juan A
• Application Number:
  US12/987,646
• Publication Number:
  US 20110222631A1
• Time in Patent Office: 1,086 Days
• Field of Search: 375/322
• US Class Current: 375/322
• CPC Class Codes: H04L 27/3863 Compensation for quadrature error in the received signal

Abstract

An apparatus for receiving a signal includes a training signal generator generating a training signal for each frequency channel; an in-phase and quadrature-phase (IQ) signal generator generating a first in-phase signal and a first quadrature-phase signal using the training signal in a first operation mode and generating a second in-phase signal and a second quadrature-phase signal using a receiving signal in a second operation mode; an IQ mismatch compensator which makes the first in-phase signal and first quadrature-phase signal generated in response to each frequency channel converge for a reference time in the first operation mode to obtain a phase mismatch compensation coefficient for selected frequency channels and after generating a look-up table using the phase mismatch compensation coefficient, compensates the second in-phase signal and the second quadrature-phase signal using the phase mismatch compensation coefficient in the second operation mode; and a memory in which the look-up table is stored.

Claims

1. An apparatus for receiving a signal, comprising:

a memory;

a training signal generator configured to generate a training signal corresponding to each of one or more frequency channels;

an in-phase and quadrature-phase (IQ) signal generator configured to generate a first in-phase signal and a first quadrature-phase signal using the training signal in a first operation mode and generate a second in-phase signal and a second quadrature-phase signal using a received signal in a second operation mode; and

an IQ mismatch compensator configured to cause the first in-phase signal and the first quadrature-phase signal generated in response to each of the one or more frequency channels to converge for a reference time in the first operation mode to obtain a phase mismatch compensation coefficient, configured to obtain the phase mismatch compensation coefficient with respect to selected frequency channels from among the one or more frequency channels and store the phase mismatch compensation coefficient in a look-up table in the memory, and configured to compensate the second in-phase signal and the second quadrature-phase signal using the phase mismatch compensation coefficient included in the look-up table in the second operation mode, after obtaining the phase mismatch compensation coefficient, wherein the IQ mismatch compensator includes,

a feedback signal combiner configured to combine an inputted in-phase signal with a feedback in-phase signal and a feedback quadrature-phase signal outputted from an in-phase and quadrature-phase mismatch compensator to generate a combined in-phase signal, and configured to combine an inputted quadrature-phase signal with the feedback in-phase signal and the feedback quadrature-phase signal outputted from an in-phase and quadrature-phase mismatch compensator to generate a combined quadrature-phase signal,

a signal determiner configured to generate a determined in-phase signal and a determined quadrature-phase signal by determining an absolute value of the combined in-phase signal and the combined quadrature-phase signal respectively, and

a mismatch compensator configured to converge the determined in-phase signal and the determined quadrature-phase signal for a reference time in the first operation mode to extract the phase mismatch compensation coefficient, and configured to apply the phase mismatch compensation coefficient to the determined in-phase signal and the determined quadrature-phase signal in the second operation mode to compensate a phase mismatch.

2. The apparatus for receiving a signal of claim 1, wherein the feedback signal combiner comprises:

a first multiplier configured to multiply an inputted in-phase signal by a feedback in-phase signal;

an inverter configured to apply a minus sign to the inputted quadrature-phase signal;

a second multiplier multiplying an output of the inverter by the feedback quadrature-phase signal;

a first adder configured to subtract an output of the second multiplier from an output of the first multiplier;

a second adder configured to generate a combined in-phase signal by subtracting an output of the first adder from the inputted in-phase signal;

a third multiplier configured to multiply an output of the inverter by the feedback in-phase signal;

a fourth multiplier configured to multiply the inputted in-phase signal by a feedback quadrature-phase signal;

a third adder configured to add outputs of the third and fourth multipliers; and

a fourth adder configured to generate a combined quadrature-phase signal by subtracting an output of the third adder from the inputted quadrature-phase signal.

3. The apparatus for receiving a signal of claim 1, wherein the signal determiner comprises:

a first absolute value operator configured to determine an absolute value of the combined in-phase signal;

a second absolute value operator configured to determine an absolute value of the combined quadrature-phase signal;

a fifth adder configured to generate a determined in-phase signal by subtracting an output of the second absolute value operator from an output of the first absolute value operator;

a first sign bit extractor configured to extract a sign bit from the combined in-phase signal;

a second sign bit extractor configured to extract a sign bit from the combined quadrature-phase signal;

an exclusive OR operator configured to perform an exclusive-OR operation on an output of the first sign bit extractor and an output of the second sign bit extractor;

a minimum value determiner configured to determine a minimum value of the output of the first absolute value operator and the output of the second absolute value operator; and

a sign setting part configured to generate a determined quadrature-phase signal by setting a sign to an output of the minimum value determiner by an output of the exclusive OR operator.

4. The apparatus for receiving a signal of claim 1, wherein the mismatch compensator comprises:

a first delay device configured to delay the determined in-phase signal for a reference time;

a sixth adder which is located at a front part of the first delay device configured to combine the determined in-phase signal with an output of the first delay device;

a first switch configured to switch the output of the first delay device to an input of the sixth adder in a first operation mode and to switch so that the phase mismatch compensation coefficient is applied to the output of the first delay device in a second operation mode;

a second delay device configured to delay the determined quadrature-phase signal for a reference time;

a seventh adder which is located at a front part the second delay device and configured to combine the determined quadrature-phase signal with an output of the second delay device;

a second switch configured to switch the output of the second delay device to an input of the seventh adder in a first operation mode and switch so that the phase mismatch compensation coefficient is applied to the output of the second delay device in a second operation mode; and

a compensation signal output device configured to extract a phase mismatch compensation coefficient converged for a reference time by controlling the first and second switches in a first operation mode and outputting an in-phase signal of which a phase mismatch is compensated and a quadrature-phase signal of which a phase mismatch is compensated by controlling the first and second switches in a second operation mode.

5. The apparatus for receiving a signal of claim 1, wherein the IQ mismatch compensator, in a second operation mode, is configured to determine a frequency channel of a receiving signal, interpolate phase mismatch compensation coefficients of at least two frequency channels adjacent to the determined frequency channel to determine a phase mismatch compensation coefficient of the determined frequency channel and output the determined phase mismatch compensation coefficient to a mismatch compensator.

6. The apparatus for receiving a signal of claim 1, wherein the memory is configured to store a phase mismatch compensation coefficient used in the receiver according to one of an initial operation and an awake operation of the receiver.

7. A method of compensating a phase mismatch, comprising:

generating a training signal corresponding to each of one or more frequency channels in a first operation mode and converging a first in-phase signal and a first quadrature-phase signal generated using the training signal for a reference time to obtain a phase mismatch compensation coefficient;

obtaining the phase mismatch compensation coefficient from channels selected in the first operation mode and generating a look-up table using the obtained phase mismatch compensation coefficients; and

compensating a phase mismatch of a second in-phase signal and a second quadrature-phase signal generated using a receiving signal in a second operation mode using the phase mismatch compensation coefficient extracted from the look-up table,

wherein obtaining the phase mismatch compensation coefficient includes,

combining the first in-phase signal and the first quadrature-phase signal with a feedback signal;

generating a combined in-phase signal and a combined quadrature-phase signal by combining the combined first in-phase signal and the combined first quadrature-phase signal with a feedback in-phase signal and a feedback quadrature-phase signal;

generating an absolute in-phase signal and an absolute quadrature-phase signal by determining an absolute value of the combined in-phase signal and the combined quadrature-phase signal, respectively;

generating a determined in-phase signal by subtracting the absolute quadrature-phase signal from the absolute in-phase signal;

determining a sign by extracting a sign from each of the combined in-phase signal and the combined quadrature-phase signal to perform an exclusive-OR operation on the extracted sign;

determining a minimum value of the absolute value in-phase signal and the absolute value quadrature phase signal;

setting the sign to the minimum value to generate a determined quadrature-phase signal; and

combining the determined in-phase signal and the combined quadrature-phase signal with a delayed in-phase signal and a delayed quadrature-phase signal and determining a phase mismatch compensation coefficient by converging for a reference time.

8. The method of claim 7, wherein compensating the phase mismatch comprises detecting phase mismatch compensation coefficients of at least two frequency channels adjacent to a frequency channel of the receiving signal interpolated from the look-up table and interpolating the detected phase mismatch compensation coefficients to determine a phase mismatch compensation coefficient.

9. An apparatus for receiving a signal, comprising:

a memory;

a training signal generator configured to generate a training signal corresponding to each of one or more frequency channels;

an in-phase and quadrature phase (IQ) signal generator configured to operate in a first operation mode and a second operation mode such that in the first operation mode, the IQ signal generator is configured to generate a first in-phase signal and a first quadrature-phase signal based on the training signal, and in the second operation mode, the IQ signal generator is configured to generate a second in-phase signal and a second quadrature-phase signal based on a receiving signal; and

an IQ mismatch compensator configured to operate in the first operation mode and the second operation mode such that, in the first operation mode, the IQ mismatch compensator is configured to obtain a phase mismatch compensation coefficient based on selected frequency channels from among the one or more frequency channels by causing the first in-phase signal and the first quadrature-phase signal to converge for a reference time, and configured to store the obtained phase mismatch compensation coefficient in a look-up table in the memory, and in the second operation mode, the IQ mismatch compensator is configured to compensate the second in-phase signal and the second quadrature-phase signal using the phase mismatch compensation coefficient included in the look-up table,

wherein the IQ mismatch compensator includes,

a feedback signal combiner configured to combine an inputted in-phase signal with a feedback in-phase signal and a feedback quadrature-phase signal outputted from an in-phase and quadrature-phase mismatch compensator to generate a combined in-phase signal, and configured to combine an inputted quadrature-phase signal with the feedback in-phase signal and the feedback quadrature-phase signal outputted from an in-phase and quadrature-phase mismatch compensator to generate a combined quadrature-phase signal,

a signal determiner configured to generate a determined in-phase signal and a determined quadrature-phase signal by determining an absolute value of the combined in-phase signal and the combined quadrature-phase signal respectively, and

a mismatch compensator configured to converge the determined in-phase signal and the determined quadrature-phase signal for a reference time in the first operation mode to extract the phase mismatch compensation coefficient, and configured to apply the phase mismatch compensation coefficient to the determined in-phase signal and the determined quadrature-phase signal in the second operation mode to compensate a phase mismatch.