Multi-processor device with groups of processors and respective separate external bus interfaces

• US 8,621,127 B2
• Filed: 05/15/2012
• Issued: 12/31/2013
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ishimi, Koichi
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US13/471,968
• Publication Number:
  US 20120226847A1
• Time in Patent Office: 595 Days
• Field of Search: 710/306, 710/307, 710/313, 710/315, 712/29
• US Class Current: 710/306
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Claims

1. A semiconductor device comprising:

a plurality of processors formed over a single chip and including a plurality of a first type of processors disposed in a first layout region of the single chip in plan view and a plurality of a second type of processors disposed separately from the plurality of the first, type of processors in a second layout region of the single chip in plan view, each said first type of processor having a first architecture, and each said second type of processor having a second architecture which is different from the first architecture of said first type of processor;

a first bus which is disposed in the first layout region of the single chip and to which each of the plurality of the first type of processors is coupled;

a second bus which is disposed in the first layout region of the single chip and to which each of the plurality of the second type of processors is coupled;

a first external bus interface to which the first bus is coupled;

a second external bus interface to which the second bus is coupled;

a plurality of first voltage supply lines arranged along one direction in the first layout region of the single chip in plan view with a space of a first width between adjacent ones of said first voltage supply lines, each said first voltage supply line having a second width in said one direction; and

a plurality of second voltage supply lines arranged along said one direction in the second layout region of the single chip in plan view with a space of a third width, which is larger than the first width, between adjacent ones of said second voltage supply lines, each said second voltage supply line having a fourth width, which is smaller than the second width, in said one direction,

wherein, in plan view, the first external bus interface is disposed at a first edge of the single chip and the second external bus interface is disposed at a second edge of the single chip different from the first edge,

wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled using separate clocks which differ in frequency or phase,

wherein the first external bus interface is coupled to a first external bus and the second external bus interface is coupled to a second external bus,

wherein the plurality of the first type of processors are configured to access the first external bus via the first bus and the first external bus interface and to access the second external bus via the first bus, the second bus, and the second external bus interface, and

wherein the plurality of the second type of processors are configured to access the second external bus via the second bus and the second external bus interface.

2. The semiconductor device according to claim 1,

wherein the first layout region is controlled using a high frequency clock, and the second layout region is controlled using a low frequency clock.

3. The semiconductor device according to claim 1,

wherein the first layout region is controlled using a high frequency clock and the second layout region is controlled using a low frequency clock, and

wherein the first layout region has a larger number of voltage supply terminals than the second layout region.

4. The semiconductor device according to claim 1, further comprising a secondary cache formed over the single chip that couples the first bus and the second bus to each other.

5. The semiconductor device according to claim 4,

wherein said secondary cache is located between the first bus and the first external bus interface.

6. The semiconductor device according to claim 1,

wherein the first voltage supply lines have a first impedance, and the second voltage supply lines have a second impedance, and

wherein the first impedance is lower than the second impedance, and, as between the first and second layout regions, only the first layout region has the first voltage supply lines having the first impedance.

7. A semiconductor device comprising:

a plurality of a first type of processors disposed in a first layout region of a single chip in plan view, the single chip having a rectangular shape with four sides in plan view;

a plurality of a second type of processors disposed separately from the plurality of the first type of processors in a second layout region of the single chip in plan view, each said second type of processor having a different architecture from said first type of processor;

a first bus provided over the single chip, and being disposed in the first layout region of the single chip in plan view and to which the plurality of the first type of processors is coupled;

a second bus provided over the single chip, and being disposed in the second layout region of the single chip in plan view and to which the plurality of the second type of processors is coupled;

a first external bus interface provided over the single chip, to which the first bus is coupled;

a second external bus interface provided over the single chip, to which the second bus is coupled;

a plurality of first voltage supply lines arranged along one direction in the first layout region of the signal chip in plan view with a space of a first width between adjacent ones of said first voltage supply lines, each first voltage supply line having a second width in said one direction; and

a plurality of second voltage supply lines arranged along said one direction in the second layout region of the single chip in plan view with a space of a third width, which is larger than the first width, between adjacent ones of said second voltage supply lines, each said second voltage supply line having a fourth width, which is smaller than the second width, in said one direction,

wherein, in plan view, the first external bus interface has a portion disposed closer to a first side of the four sides of the single chip than to the other three sides, and the second external bus interface has a portion disposed closer to a second side of the four sides of the single chip than to the other three sides, said second side being a different side from the first side,

wherein the plurality of the first type of processors and the plurality of the second type of processors are controlled using separate clocks which differ in frequency or phase,

wherein the first external bus interface is coupled to a first external bus and the second external bus interface is coupled to a second external bus,

wherein the plurality of the first type of processors are configured to access the first external bus via the first bus and the first external bus interface and to access the second external bus via the first bus, the second bus, and the second external bus interface, and

wherein the plurality of the second type of processors are configured to access the second external bus via the second bus and the second external bus interface.

8. The semiconductor device according to claim 7,

wherein the plurality of the first type of processors are controlled using a high frequency clock, and the plurality of the second type of processors are controlled using a low frequency clock.

9. The semiconductor device according to claim 7,

wherein the first layout region is controlled using a high frequency clock, and the second layout region is controlled using a low frequency clock, and

wherein the first layout region has a larger number of voltage supply terminals than the second layout region.

10. The semiconductor device according to claim 7, further comprising a secondary cache provided over the single chip that couples the first bus and the second bus to each other.

11. The semiconductor device according to claim 10,

wherein said secondary cache is arranged between the first bus and the first external bus interface.

12. The semiconductor device according to claim 7,

wherein said first external bus interface has another portion disposed closer to a third side of said four sides of the single chip than to the other four sides of the single chip in plan view, said third side being a different side from said first and second sides and being adjacent to said first side.

13. The semiconductor device according to claim 7,

wherein the first voltage supply lines have a first impedance, and the second voltage supply lines have a second impedance, and wherein the first impedance is lower than the second impedance, and, as between the first and second layout regions, only the first layout region has the first voltage supply lines having the first impedance.