Metadata rebuild in a flash memory controller following a loss of power

• US 8,621,137 B2
• Filed: 04/08/2008
• Issued: 12/31/2013
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/082,222
• Publication Number:
  US 20090172262A1
• Time in Patent Office: 2,093 Days
• Field of Search: 711/5, 711/14, 711/147, 711/169, 710/317
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A method of rebuilding metadata in a flash memory controller following a loss of power. The method includes reading logical address information associated with an area of flash memory, and using time stamp information to determine if data stored in the flash memory area is valid.

Claims

1. A method of rebuilding metadata used in a flash memory controller following a loss of power, comprising:

(a) copying from flash memory to volatile memory a first table containing metadata regarding a first block in flash memory, each block comprising a plurality of pages of flash memory, wherein the first table contains logical addresses for each of a sequence of physical locations in flash memory;

(b) based on one or more indicators, determining whether the first block in flash memory was open for writing, closed for writing or erased at the time of power loss;

(c) if the first block was erased, placing an identifier of the first block in a memory structure that contains identifications of flash memory blocks that may be written to;

(d) if the first block was closed for writing, performing the following sub-operations for each of two or more of the flash memory pages of the first block, the first table containing metadata for each such page;

(1) reading from the first table a logical address;

(2) determining whether an entry corresponding to the logical address and associated with a second block is found in a second table in volatile memory, the second table containing physical location information in flash memory for each of a sequence of logical addresses;

(3) if no such entry is found, setting a first valid bit in volatile memory to a state indicating that first data stored in a first page is valid;

(4) if such an entry is found, performing the following sub-sub-operations;

i. reading from the first table in volatile memory a first time stamp relating to a closing time of the first block;

ii. comparing the first time stamp to a second time stamp stored in volatile memory, the second time stamp relating to a closing time of the second block;

iii. if the comparison indicates that the first data was written earlier, setting the first valid bit to a state indicating that the first data is invalid;

iv. if the comparison indicates that the first data was written later, setting a second valid bit in volatile memory to a state indicating that second data is invalid;

(e) if the first block was open for writing, reading from the first block metadata associated with each page within the first block, and using the metadata to populate the first table.

2. The method of claim 1, wherein operation

(d)(3) also includes writing physical address-related information to volatile memory, the address-related information relating to the location of the first data in the flash memory.

3. The method of claim 2, wherein:

the physical address-related information is associated in the volatile memory with logical address information.

4. The method of claim 1, wherein:

operations (a)-(e) are carried out with respect to a first flash memory group made up of a plurality of flash memory devices, and

the same operations are independently carried out with respect to a second flash memory group made up of a plurality of flash memory devices, the operations on the first flash memory group and the operations on the second flash memory group overlapping in time.

5. The method of claim 4, wherein:

operations (a)-(e) are independently carried out with respect to third, fourth, fifth, sixth, seventh and eighth flash memory groups made up of a plurality of flash memory devices, the operations on all eight flash memory groups overlapping in time.

6. The method of claim 4, wherein:

each block in flash memory includes memory locations on a plurality of separate flash memory devices.

7. The method of claim 6, wherein:

each block of flash memory is erasable as a unit by the flash memory controller.

8. The method of claim 1, wherein:

each page includes separate memory locations on a plurality of separate flash memory devices.

9. The method of claim 8, wherein:

each separate memory location comprises a flash page.

10. The method of claim 3, wherein:

following the operation (e) population of the first table, performing operations (d)(1)-(4) for each page of the first block.

11. The method of claim 1, further including:

(f) copying from flash memory to volatile memory a third table containing metadata regarding a third block of flash memory;

(g) based on one or more indicators, determining whether the third block of flash memory was open for writing, closed for writing or erased at the time of power loss;

(h) if the third block was erased, placing an identifier of the third block in the memory structure that contains identifications of flash memory blocks that may be written to;

(i) if the third block was closed for writing, performing the following operations for each of two or more flash memory pages of the second block, the third table containing metadata for each such page;

(1) reading from the third table a respective logical address;

(2) determining whether an entry corresponding to the respective logical address is stored in the second table;

(3) if no such entry is found, setting a third valid bit in volatile memory to a state indicating that third data stored in the page is valid;

(4) if such an entry is found, performing the following sub-sub-operations;

i. reading from the third table in volatile memory a third time stamp relating to the relative time when the third data was written to the page;

ii. comparing the third time stamp to a fourth time stamp stored in volatile memory, the fourth time stamp relating to the relative time when fourth data was written to a different flash memory block and/or flash memory page;

iii. if the comparison indicates that the third data was written earlier, setting the third valid bit to a state indicating that the third data is invalid;

iv. if the comparison indicates that the third data was written later, setting a fourth valid bit in volatile memory to a state indicating that the fourth data is invalid;

(j) if the third block was open for writing, reading from the metadata associated with each page within the third block, and using the metadata to populate the third table.

12. The method of claim 1, wherein:

operation (d)(4)(iii) further includes writing physical address-related information to volatile memory, the physical address-related information relating to the location of the second data in the flash memory.

13. The method of claim 12, wherein:

the physical address-related information is written into a second table location in the second table.

14. The method of claim 13, wherein:

the second table location into which the physical address-related information is written is a location corresponding to the logical address.

26. The method of claim 1, further comprising an operation of comparing a third time stamp in the first metadata table to a fourth time stamp in the second metadata table when the first time stamp is equal to the second time stamp;

wherein

the third time stamp is the time when first data was written in a first page; and

the fourth time stamp is the time when second data was written in a second page.

15. A flash memory controller comprising a non-volatile storage medium, wherein the non-volatile storage medium comprises:

a processor;

a first set of instructions for execution by the processor, the first set of instructions when executed causing the flash memory controller to perform a first method for carrying out power loss recovery comprising;

copying a first metadata table from flash memory to volatile memory within the flash memory controller, the first metadata table relating to a first group of flash memory blocks and containing logical addresses for each of a sequence of physical locations in flash memory;

reading one or more valid bits and flags from the first metadata table, the valid bits and flags relating to a status of the first group at the time of power loss, wherein the one or more valid bits and flags from the first metadata table include one or more indicia indicating whether the first group was open for writing or closed for writing at the time of power loss;

if the valid bits and flags indicate that the first group contained valid data and had been closed for writing at the time of power loss, reading from the first metadata table first information relating to a portion of the first group, and using the first information to identify a first entry in a second metadata table contained in volatile memory within the flash memory controller, the second metadata table containing physical location information in flash memory for each of a sequence of logical addresses;

if the second metadata table first entry contains valid information, comparing a first time stamp with a second time stamp and overwriting the second metadata table first entry if the first time stamp is later than the second time stamp wherein

the first time stamp is updated when the first group of flash memory blocks is closed for writing and the second time stamp is updated when a group of flash memory blocks related to the second metadata table is closed for writing; and

a second set of instructions for execution by the processor, the instructions when executed causing the flash memory controller to perform a second method for carrying out power loss recovery comprising;

copying a third metadata table from flash memory to volatile memory within the flash memory controller, the third metadata table relating to a second group of flash memory blocks;

reading one or more valid bits and flags from the third metadata table, the valid bits and flags relating to a status of the second group at the time of power loss, wherein the one or more valid bits and flags from the third table include one or more indicia indicating whether the second group was open for writing or closed for writing at the time of power loss;

if the valid bits and flags indicate that the second group contained valid data and had been closed for writing at the time of power loss, reading from the third metadata table second information relating to a portion of the second group, and using the second information to identify a second entry in the second metadata table;

if the second metadata table second entry contains valid information, comparing a third time stamp with a fourth time stamp and overwriting the second metadata table second entry if the third time stamp is later than the fourth time stamp.

16. The flash memory controller of claim 15, wherein:

the first group of flash memory blocks is stored on a first set of flash memory devices and the second group of flash memory blocks is stored on a second set of flash memory devices.

17. The flash memory controller of claim 16, wherein:

the first set of flash memory devices stores data associated with a first logical address range and the second set of flash memory devices stores data associated with a second logical address range that does not overlap the first logical address range.

18. The flash memory controller of claim 15, wherein:

the first time stamp is stored in the first metadata table, and the third time stamp is stored in the third metadata table.

19. The flash memory controller of claim 15, wherein:

the first information is a first logical address and the second information is a second logical address.

20. The flash memory controller of claim 15, wherein:

the first entry includes a physical address in the first group of flash memory blocks and the second entry includes a physical address in the second group of flash memory blocks.

21. The flash memory controller of claim 16, wherein:

the first method is performed as part of a first loop that handles a plurality of portions of the first group of flash memory blocks in sequence, in each case reading from the first metadata table information relating to the portion, using that information to identify an entry in the second metadata table, comparing two time stamps and overwriting a second metadata table entry if one of the time stamps is later than the other.

22. The flash memory controller of claim 21, wherein:

each portion of the plurality of portions of the first group consists of a plurality of flash pages, each page stored on a separate flash memory device from the first set of flash memory devices, and

each portion of the plurality of portions of the second group consists of a plurality of flash pages, each page stored on a separate flash memory device from the second set of flash memory devices.

23. The flash memory controller of claim 22, wherein:

the first loop is part of a second loop which proceeds through a sequence of groups of flash memory blocks, each group being stored in the first set of flash memory devices.

24. The flash memory controller of claim 15, wherein:

the first method includes, if the valid bits and flags indicate that the first group did not contain valid data, writing an identifier of the first group to a list contained in volatile memory within the flash memory controller, the list constituting a list of groups of flash memory blocks that are available for writing.

25. The flash memory controller of claim 17, further including:

a third set of instructions for execution by the processor, the instructions when executed causing the flash memory controller to perform a third method for carrying out power loss recovery comprising;

copying a fourth metadata table from flash memory to volatile memory within the flash memory controller, the fourth metadata table relating to a third group of flash memory blocks;

reading one or more indicators from the fourth metadata table, the one or more indicators relating to a status of the third group at the time of power loss;

if the one or more indicators indicate that the third group contained valid data and had been closed for writing at the time of power loss, reading from the fourth metadata table third information relating to a portion of the third group, and using the third information to identify a third entry in the second metadata table;

if the second metadata table third entry contains valid information, comparing a fifth time stamp with a sixth time stamp and overwriting the second metadata table third entry if the fifth time stamp is later than the sixth time stamp; and

a fourth set of instructions for execution by the processor, the instructions when executed causing the flash memory controller to perform a fourth method for carrying out power loss recovery comprising;

copying a fifth metadata table from flash memory to volatile memory within the flash memory controller, the fifth metadata table relating to a fourth group of flash memory blocks;

reading one or more indicators from the fifth metadata table, the one or more indicators relating to a status of the fourth group at the time of power loss;

if the one or more indicators indicate that the fourth group contained valid data and had been closed for writing at the time of power loss, reading from the fifth metadata table fourth information relating to a portion of the fourth group, and using the fourth information to identify a fourth entry in the second metadata table;

if the second metadata table fourth entry contains valid information, comparing a seventh time stamp with an eighth time stamp and overwriting the second metadata table fourth entry if the seventh time stamp is later than the eighth time stamp;

wherein, the third group of flash memory blocks is stored on a third set of flash memory devices and the fourth group of flash memory blocks is stored on a fourth set of flash memory devices, the third set of flash memory devices stores data associated with a third logical address range, the fourth set of flash memory devices stores data associated with a fourth logical address range, and the first, second, third and fourth logical address ranges do not overlap.

27. The flash memory controller of claim 15, wherein the first set of instructions further comprises instructions for comparing a fifth time stamp in the first metadata table to a sixth time stamp in the second metadata table when the first time stamp is equal to the second time stamp;

wherein

the fifth time stamp indicates a time when first data was written in the first group of flash memory blocks; and

the sixth time stamp indicates a time when second data was written in a page related to the second metadata table.

28. A system including a flash memory controller comprising a flash memory interface for coupling to a flash memory, a system memory interface for coupling to a system memory, a host interface for coupling to a host, and a plurality of flash memory devices, the flash memory controller comprising:

a processor;

a non-volatile storage medium, the non-volatile medium further

storing a first set of instructions for execution by the processor, the first set of instructions when executed causing the flash memory controller to perform a first method for carrying out power loss recovery comprising;

copying a first metadata table from flash memory to volatile memory within the flash memory controller, the first table relating to a first group of flash memory blocks and containing logical addresses for each of a sequence of physical locations in flash memory;

reading one or more valid bits and flags from the first table, the valid bits and flags relating to a status of the first group at the time of power loss, wherein the one or more valid bits and flags from the first table include one or more indicia indicating whether the first group was open for writing or closed for writing at the time of power loss;

if the valid bits and flags indicate that the first group contained valid data and had been closed for writing at the time of power loss, reading from the first table first information relating to a portion of the first group, and using the first information to identify a first entry in a second metadata table contained in volatile memory within the flash memory controller, the second metadata table containing physical location information in flash memory for each of a sequence of logical addresses;

if the second metadata table first entry contains valid information, comparing a first time stamp with a second time stamp and overwriting the second metadata table first entry if the first time stamp is later than the second time stamp;

wherein

the first time stamp is updated when the first group of flash memory blocks is closed for writing and the second time stamp is updated when a group of flash memory blocks related to the second metadata table is closed for writing.

29. The system of claim 28, wherein the first method for carrying out power loss recovery further includes comparing a third time stamp in the first table to a fourth time stamp in the second metadata table when the first time stamp is equal to the second time stamp.

30. The system of claim 28, further comprising a second set of instructions for execution by the processor, the second set of instructions when executed causing the flash memory controller to perform a second method for carrying out power loss recovery comprising:

copying a third metadata table from flash memory to volatile memory within the flash memory controller, the third table relating to a second group of flash memory blocks;

reading one or more valid bits and flags from the third table, the valid bits and flags relating to a status of the second group at the time of power loss, wherein the one or more valid bits and flags from the third table include one or more indicia indicating whether the second group was open for writing, closed for writing, or erased at the time of power loss;

if the valid bits and flags indicate that the second group contained valid data and had been closed for writing at the time of power loss, reading from the third table second information relating to a portion of the second group, and using the second information to identify a second entry in the second metadata table;

if the second metadata table second entry contains valid information, comparing a fifth time stamp with a sixth time stamp and overwriting the second metadata table second entry if the fifth time stamp is later than the sixth time stamp.

31. The system of claim 30, wherein the first group of flash memory blocks is stored on a first set of flash memory devices and the second group of flash memory blocks is stored on a second set of flash memory devices.

32. The system of claim 31, wherein a first set of flash memory devices stores data associated with a first logical address range and a second set of flash memory devices stores data associated with a second logical address range that does not overlap the first logical address range.