Flash storage controller execute loop

• US 8,621,138 B2
• Filed: 04/08/2008
• Issued: 12/31/2013
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Tsai, Sheng-Jen
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/082,223
• Publication Number:
  US 20090172263A1
• Time in Patent Office: 2,093 Days
• Field of Search: 711/4, 711/114, 710/112
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

In a storage controller connected to a flash memory module, an execute loop used to carry out tasks related to reading or writing data from the module. The loop includes reading a data structure from a queue and carrying out a task specified by the data structure, unless resources required by the task are not available, in which event the loop moves on to another data structure stored in another queue. Data structures bypassed by the loop are periodically revisited, until all tasks required are completed. Data structures store state information that is updated when tasks are completed.

Claims

1. A method including performing the following steps by a storage controller in a system wherein the storage controller is operatively coupled to a flash memory module:

for each flash port of a plurality of flash ports, each flash port corresponding to a flash group of the flash memory module, each flash port comprising an associated processor, setting a repeat count register to a predetermined value if the flash port is in sleep mode such that the processor associated with the flash port wakes up before a transfer operation associated with the flash port is complete;

upon wake up of a first processor of a first flash port of the plurality of flash ports, prior to the transfer operation completing, in accordance with the predetermined value set in the repeat count register;

reading a first identifier of a first data structure from a first queue corresponding to a first bank of a first flash group;

reading a first state information from the first data structure, the first state information identifying a first stage of a first flash read or write command;

based on the identified first stage, identifying a first task to be accomplished or a first resource required by the first data structure, wherein the first task is related to reading data from or writing data to the first bank of the first flash group;

if the first resource is required by the first stage, checking to determine if it is available;

if the first resource is available, or if the first stage does not require resource availability, performing the first task;

modifying the first state information in the first data structure to reflect performance of the first task;

reading a second identifier of a second data structure from a second queue corresponding to a second bank of the first flash group;

reading a second state information from the second data structure, the second state information identifying a second stage of a second flash read or write command;

based on the identified second stage, identifying a second task to be accomplished or a second resource required by the second data structure, wherein the second task is related to reading data from or writing data to the second bank of the first flash group;

if the second resource is required by the second stage, checking to determine if it is available;

if the second resource is available, or if the second stage does not require resource availability, performing the second task; and

modifying the second state information in the second data structure to reflect performance of the second task; and

repeating the above steps until the first state information or the second state information indicates that the operations required by the corresponding data structure is are completed, at which point a pointer to that data structure is removed from the corresponding queue and the method continues for the other data structure until its state information indicates that the operations required by it are completed, at which point a pointer to that data structure is removed from the corresponding queue.

2. The method as in claim 1, with the storage controller performing further steps, comprising:

if the resource required by the first data structure is unavailable, skipping performance of the first task related to reading data from or writing data to the first bank of the first flash group and skipping modification of the first data structure; and

if the resource required by the second data structure is unavailable, skipping performance of the second task related to reading data from or writing data to the second bank of the first flash group and skipping modification of the second data structure.

3. The method as in claim 1, wherein:

both the first flash read or write command related to the first state information and the second flash read or write command related to the second state information relate to the same host command.

4. The method as in claim 1, wherein:

the first flash read or write command related to the first state information and the second flash read or write command related to the second state information relate to different host commands.

5. The method as in claim 1, with the storage controller performing further steps, comprising:

following removal of the pointer to the first data structure from the first queue, reading a third identifier of a third data structure from the first queue, the third data structure relating to the same host command as the first data structure.

6. The method as in claim 1, wherein:

the first task related to reading data from or writing data to the first bank of the first flash group includes transmitting command and address information to the first bank of the first flash group.

7. The method as in claim 1, wherein:

the first resource required by the first data structure comprises a first buffer, wherein the first buffer is used as a recipient of data read from the first bank of the first flash group or data to be written to the first bank of the first flash group.

8. The method as in claim 7, wherein the system also includes a volatile memory that is external to the storage controller, and wherein:

the first buffer is used as a recipient of data transferred from the volatile memory.

9. The method as in claim 8, wherein:

the second resource required by the second data structure comprises a second buffer, and, following a determination that the second buffer is available, the second buffer is used as a recipient of data read from the second bank of the first flash group or data to be written to the second bank of the first flash group.

10. The method as in claim 9, wherein:

the second buffer is used to store data to be transferred to the volatile memory.

11. The method of claim 1 further comprising the step of setting the flash port in sleep mode.

12. A system, comprising:

a storage controller configured to be coupled to a flash memory module;

a host interface configured to receive a plurality of host commands;

a plurality of processors;

memory storing one or more programs, which when executed by respective processors of the plurality of processors cause the storage controller to perform a method comprising;

for each flash port of a plurality of flash ports, each flash port corresponding to a flash group of the flash memory module, each flash port comprising an associated processor, setting a repeat count register to a predetermined value if the flash port is in sleep mode such that the processor associated with the flash port wakes up before a transfer operation associated with the flash port is complete;

upon wake up of a first processor of a first flash port of the plurality of flash ports, prior to the transfer operation completing, in accordance with the predetermined value set in the repeat count register;

reading a first identifier of a first data structure from a first queue corresponding to a first bank of a first flash group;

reading a first state information from the first data structure, the first state information identifying a first stage of a first flash read or write command;

based on the identified first stage, identifying a first task to be accomplished or a first resource required by the first data structure, wherein the first task is related to reading data from or writing data to the first bank of the first flash group;

if the first resource is required by the first stage, checking to determine if it is available;

if the first resource is available, or if the first stage does not require resource availability, performing the first task;

modifying the first state information in the first data structure to reflect performance of the first task;

reading a second identifier of a second data structure from a second queue corresponding to a second bank of the first flash group;

reading a second state information from the second data structure, the second state information identifying a second stage of a second flash read or write command;

based on the identified second stage, identifying a second task to be accomplished or a second resource required by the second data structure, wherein the second task is related to reading data from or writing data to the second bank of the first flash group;

if the second resource is required by the second stage, checking to determine if it is available;

if the second resource is available, or if the second stage does not require resource availability, performing the second task; and

modifying the second state information in the second data structure to reflect performance of the second task; and

repeating the above steps until the first state information or the second state information indicates that the operations required by the corresponding data structure is are completed, at which point a pointer to that data structure is removed from the corresponding queue and the method continues for the other data structure until its state information indicates that the operations required by it are completed at which point a pointer to that data structure is removed from the corresponding queue.

13. The system of claim 12, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the storage controller to:

if the resource required by the first data structure is unavailable, skip performance of the first task related to reading data from or writing data to the first bank of the first flash group and skip modification of the first data structure; and

if the resource required by the second data structure is unavailable, skip performance of the second task related to reading data from or writing data to the second bank of the first flash group and skip modification of the second data structure.

14. The system of claim 12, wherein:

both the first flash read or write command related to the first state information and the second flash read or write command related to the second state information relate to the same host command.

15. The system of claim 12, wherein:

the first flash read or write command related to the first state information and the second flash read or write command related to the second state information relate to different host commands.

16. The system of claim 12, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the storage controller to:

following removal of the pointer to the first data structure from the first queue, reading a third identifier of a third data structure from the first queue, the third data structure relating to the same host command as the first data structure.

17. The system of claim 12, wherein:

the first task related to reading data from or writing data to the first bank of the first flash group includes transmitting command and address information to the first bank of the first flash group.

18. The system of claim 12, wherein:

the first resource required by the first data structure comprises a first buffer, the first buffer is used as a recipient of data read from the first bank of the first flash group or data to be written to the first bank of the first flash group.

19. The system of claim 18, further including a volatile memory that is external to the storage controller, and wherein:

the first buffer is used as a recipient of data transferred from the volatile memory.

20. The system of claim 19, wherein:

the second resource required by the second data structure comprises a second buffer, and, following a determination that the second buffer is available, the second buffer is used as a recipient of data read from the second bank of the first flash group or data to be written to the second bank of the first flash group.

21. The system of claim 20, wherein:

the second buffer is used to store data to be transferred to the volatile memory.

22. The system of claim 12, wherein the one or more programs further include instructions that, when executed by the one or more processors, cause the storage controller to set the flash port in sleep mode.

23. A method including performing the following steps by a storage controller in a system wherein the storage controller is operatively coupled to a flash memory module:

for each flash port of a plurality of flash ports, each flash port corresponding to a flash group of the flash memory module, each flash port comprising an associated processor, setting a repeat count register to a predetermined value if the flash port is in sleep mode such that the processor associated with the flash port wakes up before a transfer operation associated with the flash port is complete;

upon wake up of a first processor of a first flash port of the plurality of flash ports, prior to the transfer operation completing, in accordance with the predetermined value set in the repeat count register;

determining, in succession, among each of a plurality of distinct queues, each queue corresponding to a distinct bank of a first flash group of the flash memory module, whether a respective queue includes a respective data structure;

in accordance with a determination that the respective queue includes the respective data structure, advancing the respective data structure by;

reading a respective identifier of the respective data structure from the respective queue corresponding to a respective bank of the first flash group;

reading a respective state information from the respective data structure, the respective state information identifying a respective stage of a corresponding flash read or write command;

based on the identified respective stage, identifying a respective task to be accomplished or a respective resource required by the data structure, wherein the respective task is related to reading data from or writing data to the respective bank of the first flash group;

if the respective resource is required by the respective stage, checking to determine if it is available;

if the respective resource is available, or if the respective stage does not require resource availability, performing the respective task; and

modifying the respective state information in the respective data structure to reflect performance of the respective task; and

repeating the above steps until the respective state information in the respective data structures in the plurality of distinct queues indicates that operations required by the respective data structures are completed; and

for each respective data structure, removing a pointer to the respective data structure from the corresponding queue when the corresponding state information indicates that the operations required by the respective data structure are completed.