Wirelessly configurable memory device

• US 8,621,175 B2
• Filed: 03/26/2012
• Issued: 12/31/2013
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza), Markison, Timothy W.
• Primary Examiner(s): Jiang, Charles C
• Assistant Examiner(s): KAMARA, MOHAMED A
• Application Number:
  US13/429,685
• Publication Number:
  US 20120185665A1
• Time in Patent Office: 645 Days
• Field of Search: 370/310, 370/343, 370/344, 370/329, 370/338, 711/105, 711170-171, 365/236.05, 365/189.02, 455/431, 455/41.2
• US Class Current: 711/171
• CPC Class Codes: G03G 15/6508 Automatic supply devices interacting with the rest of the apparatus, e.g. selection of a specific cassette matching the image with the size of the copy material G03G15/5095
• CPC Class Codes: G03G 15/6558 Feeding path after the copy sheet preparation and up to the transfer point, e.g. registering; Deskewing; Correct timing of sheet feeding to the transfer point
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H04M 1/72412 using two-way short-range wireless interfaces
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A configurable memory includes an interface section, a plurality of memory modules, and an internal configuration section. The interface section includes a millimeter wave (MMW) transceiver and interfaces with one or more external components. Each the plurality of memory modules includes a memory MMW transceiver and a plurality of memory cells. The internal configuration section includes a memory management unit and a memory management MMW transceiver. The memory management unit is operable to determine configuration of at least some of the plurality of memory modules to form a memory block, identify an interface MMW transceiver to provide a wireless link to the memory block, and generate a configuration signal based on the determined configuration and the identified interface MMW transceiver. The memory management MMW transmits the MMW configuration signal to the identified interface MMW transceiver and the MMW transceivers of the memory modules.

Claims

1. A configurable memory, comprising:

a plurality of memory modules in the configurable memory, wherein the plurality of memory modules includes memory MMW transceivers and a plurality of memory cells; and

an internal configuration section that includes a memory management millimeter wave (MMW) wireless transceiver, wherein the internal configuration section is configured to;

select a set of the plurality of memory modules to form a memory block in the configurable memory;

identify one or more memory MMW transceivers from a plurality of MMW transceivers to support the memory block; and

generate a configuration signal including configuration information for the selected set of the plurality of memory modules to form the memory block and the identified one or more memory MMW transceivers to support the memory block;

convert the configuration signal into a MMW wireless configuration signal; and

transmit the MMW wireless configuration signal by the management MMW wireless transceiver to the one or more memory MMW transceivers for the selected set of the plurality of memory modules to form the memory block and the identified one or more memory MMW transceivers to support the memory block.

2. The configurable memory of claim 1, wherein the internal configuration section is configured to select the set of the plurality of memory modules to form the memory block in the configurable memory by:

receiving a configuration command that defines size and data format of the memory block;

determining a number of memory modules based on the size;

allocating the set of the plurality of memory modules in accordance with the number of memory modules; and

determining arrangement of the set of the plurality of memory modules based on the size and the data format.

3. The configurable memory of claim 1, wherein the internal configuration section is configured to select the set of the plurality of memory modules to form the memory block in the configurable memory by:

receiving a write request;

determining size of data to be written based on the write request;

determining a number of memory modules based on the size of data; and

allocating the set of the plurality of memory modules in accordance with the number of memory modules.

4. The configurable memory of claim 1, wherein the memory MMW transceiver in the memory module of the set of the plurality of memory modules comprises:

a MMW receiver section configured to;

receive a MMW memory access signal;

convert the MMW memory access signal into an inbound symbol stream;

a baseband processing module configured to;

recover a memory access request from the inbound symbol stream;

coordinate execution of the memory access request with the plurality of memory cells;

generate a memory execution response when required; and

convert the memory execution response into the outbound symbol stream; and

a MMW transmitter section configured to;

convert an outbound symbol stream into a MMW memory response signal; and

transmit the MMW memory response signal.

5. The configurable memory of claim 1, further comprising:

one or more interface sections, wherein an interface section includes one or more millimeter wave (MMW) transceivers;

wherein the internal configuration section is configured to identify at least one interface section to a wireless link to the memory block;

wherein the memory management MMW transceiver is configured to transmit the MMW configuration signal to the at least one identified interface section.

6. The configurable memory of claim 5, wherein the memory MMW transceiver in the memory module of the set of the plurality of memory modules comprises:

a MMW front end configured to;

receive a MMW memory access signal from the at least one identified interface section;

convert the MMW memory access signal into an inbound symbol stream;

convert an outbound symbol stream into a MMW memory response signal; and

transmit the MMW memory response signal to the at least one identified interface section; and

a baseband processing module configured to;

recover a memory access request from the inbound symbol stream;

coordinate execution of the memory access request with the plurality of memory cells;

generate a memory execution response when required; and

convert the memory execution response into the outbound symbol stream.

7. The configurable memory of claim 5, wherein the plurality of memory cells are arranged in a plurality of rows;

and

wherein the memory MMW transceiver in the memory module of the set of the plurality of memory modules includes a baseband processing module and a plurality of MMW front ends, wherein a MMW front end of the plurality of MMW front ends is configured to;

receive a MMW memory access signal from the at least one identified interface section for a corresponding row of the plurality of rows;

convert the MMW memory access signal into a baseband or near baseband inbound symbol stream;

convert a baseband or near baseband outbound symbol stream into a MMW memory response signal; and

transmit the MMW memory response signal to the interface MMW transceiver; and

the baseband processing module functions to;

recover a memory access request from the baseband or near baseband inbound symbol stream;

coordinate execution of the memory access request with the corresponding row of the plurality of rows;

generate a memory execution response when required; and

convert the memory execution response into the baseband or near baseband outbound symbol stream.

8. The configurable memory of claim 1 further comprising;

a die that supports at least the plurality of memory modules and the internal configuration section; and

a package substrate that supports at least the die.

9. The configurable memory of claim 1 further comprising:

millimeter wave shielding proximal to the die and the package substrate.

10. A memory module, comprising:

an array of memory cells having a plurality of bit lines and a plurality of word lines; and

a millimeter wave (MMW) transceiver coupled to the array, wherein the MMW transceiver is configured to receive a MMW wireless memory access signal; and

one or more a processing modules configured to;

convert the MMW wireless memory access signal into a memory access request;

determine a location within the array to access based on the memory access request; and

access the location within the array via corresponding bit lines of the plurality of bit lines and corresponding word lines of the plurality of word lines in accordance with the memory access request.

11. The memory module of claim 10, wherein the memory access request is a memory read request;

and

wherein the processing module is further configured to;

retrieve data from the location within the array in accordance with the memory read request; and

convert the retrieved data into an outbound symbol stream formatted in accordance with a wireless protocol; and

wherein the MMW transceiver further functions to;

convert the outbound symbol stream into a MMW retrieved data signal; and

transmit the MMW retrieved data signal.

12. The memory module of claim 10 wherein the memory access request is a memory write request, wherein the memory write request includes data to be stored;

and the processing module is further configured to;

determine a location within the array of memory cells to store the data based on the memory write request; and

provide the data to the location within the array of memory cells via corresponding bit lines of the plurality of bit lines and corresponding word lines of the plurality of word lines.

13. The memory module of claim 10, wherein the array of memory cells comprises:

a multiplexer coupled to the plurality of bit lines;

a sense amplifier coupled to an output of the multiplexer; and

a latch coupled to an output of the sense amplifier.

14. The memory module of claim 10, wherein the processing module comprises:

a multiplexer coupled to the plurality of bit lines;

a sense amplifier coupled to an output of the multiplexer; and

a latch coupled to an output of the sense amplifier.

15. A configurable memory device, comprising:

a plurality of memory modules, wherein at least one or more of the plurality of memory modules includes;

a plurality of memory lines;

a MMW front-end, wherein the MMW front-end is configured to;

receive a MMW signal including a memory access request;

convert the MMW signal into an inbound symbol stream; and

a processing module configured to;

recover the memory access request from the inbound symbol stream;

determine a location within the plurality of memory lines to access based on the memory access request;

access the location via at least one of the plurality of memory lines in accordance with the memory access request.

16. The configurable memory device of claim 15, wherein the memory access request includes a memory read request;

and

wherein the processing module is configured to;

recover the memory read request from the inbound symbol stream;

determine a location within the plurality of memory lines to access based on the memory read request;

access the location via at least one of the plurality of memory lines in accordance with the memory read request;

receive retrieved data from the at least one of the plurality of memory lines in accordance with the memory read request; and

convert the retrieved data into an outbound symbol stream formatted in accordance with a wireless protocol; and

wherein the MMW front-end is further configured to;

convert the outbound symbol stream into a MMW retrieved data signal; and

transmit the MMW retrieved data signal.

17. The configurable memory device of claim 15 wherein the memory access request includes a memory write request, wherein the memory write request includes data to be stored;

and

wherein the processing module is configured to;

recover the memory write request from the inbound symbol stream;

determine a location within the plurality of memory lines to access based on the memory write request;

access the location via at least one of the plurality of memory lines in accordance with the memory write request; and

provide the data to be stored to the at least one of the plurality of memory lines.

18. The configurable memory device of claim 15, wherein the processing module comprises:

a sense amplifier coupled to the plurality of memory lines; and

a latch coupled to an output of the sense amplifier.

19. The configurable memory device of claim 15, wherein the at least one or more of the plurality of memory modules further comprises:

a second plurality of memory lines;

a second MMW front-end configured to;

receive a second MMW memory access signal;

convert the second MMW memory access signal into an inbound symbol stream;

a second processing module configured to;

recover the second memory access request from the inbound symbol stream; and

access the second plurality of memory lines in accordance with the second memory access request.

20. The configurable memory device of claim 15, wherein the array of memory cells comprises:

a multiplexer coupled to the plurality of memory lines;

a sense amplifier coupled to an output of the multiplexer; and

a latch coupled to an output of the sense amplifier.