Timing closure methodology including placement with initial delay values

• US 8,621,403 B2
• Filed: 04/19/2004
• Issued: 12/31/2013
• Est. Priority Date: 12/24/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation, Synopsys Incorporated
• Original Assignee: International Business Machines Corporation, Synopsys Incorporated
• Inventors: Kudva, Prabhakar, van Ginneken, Lukas P. P. P.
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/828,547
• Publication Number:
  US 20050120319A1
• Time in Patent Office: 3,543 Days
• Field of Search: 716 4- 12, 716/1, 716/2, 716/104, 716118-126, 716/100, 716/101, 716/110, 716/132
• US Class Current: 716/100
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/27 using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Claims

1. An automated method for designing an integrated circuit layout with a computer, comprising:

in a logic design phase;

mapping a digital circuit to selected cells from a cell library to implement a circuit path;

determining initial delay values and corresponding gain for the selected cells prior to assignment of wire loads based on an initial placement of the circuit path;

determining an adjusted initial delay value and corresponding gain for at least one of the selected cells prior to the assignment of wire loads based on the initial placement of the circuit path, by performing at least one of;

compressing the initial delay value of at least one of the selected cells to meet delay constraints for the circuit path, and

stretching the initial delay value of at least one of the selected cells to reduce slack in the circuit path; and

in a physical design phase;

performing the initial placement of the selected cells for the circuit path, and the assignment of wire loads to the selected cells based on the initial placement;

adjusting size or area of one or more of the selected cells during or after the initial placement, to maintain the initial delay value of the selected cells originally from the cell library; and

routing the selected cells for the circuit path.

2. The automated method of claim 1 wherein said initial delay values are determined during library analysis.

3. The automated method of claim 1, including prior to the initial placement, inserting a buffer in the circuit path when there is available slack in the circuit path.

4. The automated method of claim 3, including prior to the initial placement, determining net weight values for the selected cells, the net weight values representing sensitivity of total area of a circuit design to load on the corresponding cell, and determining whether to insert a buffer on the output of a given cell in the selected cells using the net weight value of the given cell.

5. An automated method for designing an integrated circuit layout with a computer, comprising:

in a logic design phase;

selecting cells from a cell library to implement a circuit path;

determining initial delay values and corresponding gain for the selected cells prior to assignment of wireloads based on an initial placement of the circuit path;

determining an adjusted initial delay value and corresponding gain for at least one of the selected cells prior to the assignment of wire loads based on the initial placement of the circuit path, by performing at least one of;

compressing the initial delay value of at least one of the selected cells to meet delay constraints for the circuit path, and

stretching the initial delay value of at least one of the selected cells to reduce slack in the circuit path; and

in a physical design phase;

performing the initial placement of the selected cells for the circuit path, and the assignment of wire loads to the selected cells based on the initial placement;

adjusting size or area of one or more of the selected cells during or after the initial placement to maintain the initial delay value or the adjusted initial delay value for the corresponding selected cells;

routing the selected cells for the circuit path; and

further including

determining net weight values for the selected cells, the net weight values representing sensitivity of total area of a circuit design to load on the corresponding cell, and prior to placement of the circuit path, determining whether to insert a buffer on the output of a given cell in the selected cells using the net weight value of the given cell, and inserting a buffer in the circuit path when there is available slack in the circuit path.