Semiconductor device and method for manufacturing the same

• US 8,624,237 B2
• Filed: 07/29/2009
• Issued: 01/07/2014
• Est. Priority Date: 07/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Miyairi, Hidekazu, Miyanaga, Akiharu, Akimoto, Kengo, Shiraishi, Kojiro
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Kim, Sun M
• Application Number:
  US12/511,291
• Publication Number:
  US 20100025679A1
• Time in Patent Office: 1,623 Days
• Field of Search: 257/43, 257/E29.296, 438/104
• US Class Current: 257/43
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Claims

1. A semiconductor device including a thin film transistor, the thin film transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer;

a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer;

a source electrode layer over the first n-type buffer layer, and a drain electrode layer over the second n-type buffer layer;

a third buffer layer between the semiconductor layer and the first n-type buffer layer; and

a fourth buffer layer between the semiconductor layer and the second n-type buffer layer,

wherein each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor containing indium, gallium, and zinc,

wherein each of the first n-type buffer layer and the second n-type buffer layer has higher carrier concentration than the semiconductor layer,

wherein each of the first n-type buffer layer and the second n-type buffer layer contains one selected from the group consisting of magnesium, aluminum and titanium, and

wherein each of the third buffer layer and the fourth buffer layer has a carrier concentration which is higher than that of the semiconductor layer and lower than that of each of the first n-type buffer layer and the second n-type buffer layer.

2. The semiconductor device according to claim 1, wherein each of the first n-type buffer layer and the second n-type buffer layer contains an impurity element imparting n-type conductivity.

3. The semiconductor device according to claim 1, wherein a carrier concentration of the semiconductor layer is less than 1×

10¹⁷ atoms/cm³ and each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is 1×

10¹⁸ atoms/cm³ or higher.

4. The semiconductor device according to claim 1, wherein the source electrode layer and the drain electrode layer contain titanium.

5. The semiconductor device according to claim 1, further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with an upper surface of the source electrode layer, an upper surface of the drain electrode layer, and a region of the semiconductor layer between the source electrode layer and the drain electrode layer.

6. The semiconductor device according to claim 1,

wherein the gate electrode layer comprises copper,

wherein the gate insulating layer comprises a first layer, a second layer and a third layer, and

wherein each of the first layer, the second layer and the third layer comprises silicon and nitrogen.

7. A semiconductor device including a thin film transistor, the thin film transistor comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

a semiconductor layer over the gate insulating layer;

a first n-type buffer layer and a second n-type buffer layer over the semiconductor layer;

a source electrode layer over the first n-type buffer layer, and a drain electrode layer over the second n-type buffer layer;

a third buffer layer between the semiconductor layer and the first n-type buffer layer; and

a fourth buffer layer between the semiconductor layer and the second n-type buffer layer,

wherein each of the semiconductor layer, the first n-type buffer layer and the second n-type buffer layer comprises oxide semiconductor containing indium, gallium, and zinc,

wherein a region of the semiconductor layer between the first n-type buffer layer and the second n-type buffer layer is thinner than a region of the semiconductor layer under the first n-type buffer layer and a region of the semiconductor layer under the second n-type buffer layer,

wherein each of the first n-type buffer layer and the second n-type buffer layer has higher carrier concentration than the semiconductor layer,

wherein each of the first n-type buffer layer and the second n-type buffer layer contains one selected from the group consisting of magnesium, aluminum and titanium, and

wherein each of the third buffer layer and the fourth buffer layer has a carrier concentration which is higher than that of the semiconductor layer and lower than that of each of the first n-type buffer layer and the second n-type buffer layer.

8. The semiconductor device according to claim 7, wherein each of the first n-type buffer layer and the second n-type buffer layer contains an impurity element imparting n-type conductivity.

9. The semiconductor device according to claim 7, wherein a carrier concentration of the semiconductor layer is less than 1×

10¹⁷ atoms/cm³ and each carrier concentration of the first n-type buffer layer and the second n-type buffer layer is 1×

10¹⁸ atoms/cm³ or higher.

10. The semiconductor device according to claim 7, wherein the source electrode layer and the drain electrode layer contain titanium.

11. The semiconductor device according to claim 7, further comprising an insulating layer over the source electrode layer and the drain electrode layer, wherein the insulating layer is in contact with an upper surface of the source electrode layer, an upper surface of the drain electrode layer, and a region of the semiconductor layer between the source electrode layer and the drain electrode layer.

12. The semiconductor device according to claim 7,

wherein the gate electrode layer comprises copper,

wherein the gate insulating layer comprises a first layer, a second layer and a third layer, and

wherein each of the first layer, the second layer and the third layer comprises silicon and nitrogen.