Top gate thin film transistor and display apparatus including the same
First Claim
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1. A top gate thin film transistor, comprising on a substrate:
- a source electrode layer;
a drain electrode layer;
an oxide semiconductor layer;
a gate insulating layer;
a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and
a protective layer containing hydrogen, wherein;
the gate insulating layer is formed on a channel region of the oxide semiconductor layer;
the gate electrode layer is formed on the gate insulating layer;
the protective layer is formed on the gate electrode layer and a region except the channel region of the oxide semiconductor layer; and
a width of the gate insulating layer is smaller than a width of the oxide semiconductor layer in a channel length direction.
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Abstract
Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.
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Citations
5 Claims
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1. A top gate thin film transistor, comprising on a substrate:
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a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, wherein; the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; the protective layer is formed on the gate electrode layer and a region except the channel region of the oxide semiconductor layer; and a width of the gate insulating layer is smaller than a width of the oxide semiconductor layer in a channel length direction. - View Dependent Claims (2, 3, 4, 5)
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Specification
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Current AssigneeCanon Kabushiki Kaisha (Canon Inc.)
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Original AssigneeCanon Kabushiki Kaisha (Canon Inc.)
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InventorsSato, Ayumu, Kumomi, Hideya, Yabuta, Hisato, Hayashi, Ryo, Takai, Yasuyoshi
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Primary Examiner(s)FOURSON III, GEORGE R
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Application NumberUS13/188,215Publication NumberTime in Patent Office901 DaysField of Search257/43, 257/E29.273US Class Current257/43CPC Class CodesH01L 29/66969 of devices having semicondu...H01L 29/78618 characterised by the drain ...H01L 29/78648 arranged on opposing sides ...H01L 29/7869 having a semiconductor body...
