Display device and method of manufacturing the same

• US 8,624,246 B2
• Filed: 01/31/2011
• Issued: 01/07/2014
• Est. Priority Date: 04/05/2010
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: You, Chun-Gi
• Primary Examiner(s): Tran, Minh-Loan T
• Assistant Examiner(s): Erdem, Fazli
• Application Number:
  US13/017,362
• Publication Number:
  US 20110240999A1
• Time in Patent Office: 1,072 Days
• Field of Search: None
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A display device and a method of manufacturing the same. In one embodiment, a display device includes a substrate having a pixel region, a transistor region and a capacitor region, a transistor arranged within the transistor region of the substrate and a capacitor arranged within the capacitor region of the substrate, wherein the capacitor includes a lower electrode arranged on the substrate, a gate insulating layer arranged on the lower electrode and an upper electrode arranged on the gate insulating layer and overlapping the lower electrode, the upper electrode includes a first conductive layer and a second conductive layer arranged on the first conductive layer, wherein the first conductive layer is opaque.

Claims

1. A display device, comprising:

a substrate having a pixel region, a transistor region and a capacitor region;

a transistor arranged within the transistor region of the substrate; and

a capacitor arranged within the capacitor region of the substrate, wherein the capacitor comprises;

a lower electrode arranged on the substrate;

a gate insulating layer arranged on the lower electrode; and

an upper electrode arranged on the gate insulating layer and overlapping the lower electrode, the upper electrode including a first conductive layer and a second conductive layer arranged on the first conductive layer, wherein the first conductive layer is opaque,

wherein the first conductive layer of the upper electrode comprises an impurity,

the transistor comprises a gate electrode that includes a second conductive layer arranged on a first conductive layer, the first conductive layer comprising an impurity; and

a concentration of the impurity within the first conductive layer of the gate electrode is lower than that of the concentration of the impurity within the first conductive layer of the lower electrode.

2. The display device according to claim 1, wherein the lower electrode of the capacitor is comprised of a silicon layer doped with impurity ions, the silicon layer being selected from a group consisting of amorphous silicon and poly-silicon.

3. The display device according to claim 1, wherein the first conductive layer of the upper electrode has a thickness of about 200 to 700 Å

.

4. The display device according to claim 1, wherein the first conductive layer of the upper electrode includes an element selected from a group consisting of chrome and molybdenum.

5. The display device according to claim 1, wherein the second conductive layer of the upper electrode is arranged on at least a portion of the first conductive layer.

6. The display device according to claim 5, wherein the one portion is an edge portion.

7. The display device according to claim 1, wherein the second conductive layer of the upper electrode is arranged on opposite edge portions of the first conductive layer of the upper electrode.

8. The display device according to claim 1, wherein the second conductive layer of the upper electrode includes a material selected from a group consisting of a metal and a metal alloy.

9. The display device according to claim 1, wherein the upper electrode is arranged on a same layer as the gate electrode of the transistor.

10. The display device of claim 9, wherein each of the upper electrode and the gate electrode are both arranged directly on the gate insulating layer.

11. The display device of claim 9, wherein each of the upper electrode and the gate electrode are both arranged directly on the gate insulating layer, are both comprised of same materials, and are both produced at a same time.

12. The display device of claim 1, wherein the lower electrode of the capacitor is arranged directly on a same layer as an active layer of the transistor and are both comprised of a same material.

13. The display device of claim 1, wherein the transistor comprises a gate electrode, an active layer comprised of either amorphous silicon or polysilicon, and a gate insulating layer interposed between the gate electrode and the active layer and also being interposed between the upper and lower electrodes of the capacitor, the gate electrode also comprising the first conductive layer and the second conductive layer.

14. A display device, comprising:

a substrate having a pixel region, a transistor region and a capacitor region;

a transistor arranged within the transistor region of the substrate and including a gate insulating layer interposed between a gate electrode and an active layer; and

a capacitor arranged within the capacitor region of the substrate, wherein the capacitor comprises;

a lower electrode arranged directly on a same layer and being comprised of a same material as the active layer of the transistor; and

an upper electrode arranged directly on a same layer and being comprised of same materials as the gate electrode of the transistor, wherein the gate insulating layer is also interposed between the upper electrode and the lower electrode, wherein each of the gate electrode and the upper electrode are comprised of a first conductive layer and a second conductive layer arranged on the first conductive layer, the first conductive layer being opaque and having a thickness in the range of about 200 to 700 Å

, wherein an opening is arranged in the second conductive layer of the upper electrode of the capacitor to expose the first conductive layer, wherein the first conductive layer of the upper electrode and the lower electrode of the capacitor are doped with a same impurity, the first conductive layer being comprised of at least one of chrome and molybdenum.

15. The display device of claim 14, further comprising:

an interlayer insulating layer arranged on the gate electrode and the upper electrode;

source and drain electrodes arranged on the interlayer insulating layer, the source and drain electrodes being electrically connected to source and drain regions respectively of the active layer through apertures in each of the interlayer insulating layer and the gate insulating layer;

a passivation layer arranged on the source and drain electrodes, and

a pixel electrode arranged on the passivation layer and being electrically connected to one of the source and drain electrodes through an aperture in the passivation layer.

16. The display device of claim 14, further comprising:

an interlayer insulating layer arranged on the gate electrode and the upper electrode;

source and drain electrodes arranged on the interlayer insulating layer, the source and drain electrodes being electrically connected to source and drain regions respectively of the active layer through apertures in each of the interlayer insulating layer and the gate insulating layer;

a passivation layer arranged on the source and drain electrodes, and

a pixel electrode arranged on the passivation layer and being electrically connected to one of the source and drain electrodes through an aperture in the passivation layer.