Stacked bit line dual word line nonvolatile memory
First Claim
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1. A memory device, comprising:
- a substrate;
first and second conductive lines over the substrate;
a first plug coupled to the first conductive line, and orthogonal to the first conductive line and the substrate;
a second plug coupled to the second conductive line, and orthogonal to the second conductive line and the substrate;
a first memory cell disposed on a first sidewall beside the first plug, the first sidewall being orthogonal to the substrate; and
a second memory cell disposed on a second sidewall beside the second plug, the second sidewall being orthogonal to the substrate, wherein the first memory cell is over the second memory cell.
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Abstract
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
17 Citations
11 Claims
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1. A memory device, comprising:
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a substrate; first and second conductive lines over the substrate; a first plug coupled to the first conductive line, and orthogonal to the first conductive line and the substrate; a second plug coupled to the second conductive line, and orthogonal to the second conductive line and the substrate; a first memory cell disposed on a first sidewall beside the first plug, the first sidewall being orthogonal to the substrate; and a second memory cell disposed on a second sidewall beside the second plug, the second sidewall being orthogonal to the substrate, wherein the first memory cell is over the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory device, comprising:
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a first conductive line; a second conductive line orthogonal to the first conductive line; a plug coupled to the first conductive line, and orthogonal to the first and second conductive lines; and a memory cell disposed on a sidewall beside the plug, and between the second conductive line and the plug; wherein the second conductive line comprises material having a conductivity type opposite a conductivity type of material of the plug; and wherein the second conductive line comprises polysilicon having a first conductivity type, and the plug comprises polysilicon having a second conductivity type opposite the first conductivity type. - View Dependent Claims (9, 10, 11)
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Specification