Cooling channels in 3DIC stacks

• US 8,624,360 B2
• Filed: 11/11/2009
• Issued: 01/07/2014
• Est. Priority Date: 11/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kai-Ming, Hsiao, Ching-Wen, Wang, Tsung-Ding, Tseng, Ming-Hong, Chen, Chen-Shien
• Primary Examiner(s): Luu, Chuong A.
• Application Number:
  US12/616,562
• Publication Number:
  US 20100117201A1
• Time in Patent Office: 1,518 Days
• Field of Search: 438/273, 438/531, 257/621, 257/777, 257/723, 257/724, 257/686, 257/774
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/46 involving the transfer of heat by flowing fluids H01L23/42, H01L23/44 take precedence
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

Claims

1. An integrated circuit structure comprising:

a first die comprising;

a first semiconductor substrate;

first dielectric layers over the first semiconductor substrate;

a first interconnect structure in the first dielectric layers;

a first plurality of channels extending from inside the first semiconductor substrate to inside the first dielectric layers;

a first dielectric film over the first interconnect structure and sealing top ends of the first plurality of channels, wherein a bottom surface of the first dielectric film is exposed to the first plurality of channel, and wherein the first plurality of channels is configured to allow a fluid to flow through; and

a first fluidic tube and a second fluidic tube, each attached to a bottom end of one of the plurality of channels, with inner spaces of the fluidic tubes forming a continuous space with the first plurality of channels, wherein the first fluidic tube and the second fluidic tube are underlying the semiconductor substrate.

2. The integrated circuit structure of claim 1, wherein the first plurality of channels connects the first fluidic tube to the second fluidic tube.

3. The integrated circuit structure of claim 1, wherein both a first one of the first plurality of channels connected to the first fluidic tube and a second one of the first plurality of channels connected to the second fluidic tube penetrate from a front side of the first semiconductor substrate to a backside of the first semiconductor substrate.

4. The integrated circuit structure of claim 1, wherein at least a portion of the first plurality of channels is vertically limited between a passivation layer of the first dielectric layer and the first dielectric film.

5. The integrated circuit structure of claim 1, wherein the first dielectric film is a photosensitive film.

6. The integrated circuit structure of claim 1 further comprising a second die bonded to a backside of the first semiconductor substrate in the first die.

7. The integrated circuit structure of claim 6, wherein the second die further comprises:

a second semiconductor substrate;

a second interconnect structure in second dielectric layers and on a front side of the second semiconductor substrate;

a second plurality of channels extending from inside the second semiconductor substrate to inside the second dielectric layers, wherein an inner space of the second plurality of channels is connected to an inner space of the first plurality of channels; and

a second dielectric film covering the second interconnect structure and sealing portions of the second plurality of channels.

8. The integrated circuit structure of claim 6, wherein the second die further comprises:

a second semiconductor substrate; and

a second interconnect structure in second dielectric layers and on a front side of the second semiconductor substrate, wherein no channel is formed in the second dielectric layers and connected to the first plurality of channels.

9. The integrated circuit structure of claim 1, wherein the first plurality of channels comprises a first portion in a first layer of the first dielectric layers, and a second portion in a second layer of the first dielectric layers, and wherein the first portion does not vertically overlap the second portion.

10. The integrated circuit structure of claim 9 further comprising a shaft in the first interconnect structure, with an inner space in the shaft being part of the first plurality of channels.

11. An integrated circuit structure comprising:

a first die comprising;

a first semiconductor substrate;

a first interconnect structure comprising metal lines and vias in first dielectric layers and on a front side the first semiconductor substrate;

a first opening and a second opening extending from the front side to a backside of the first semiconductor substrate; and

a first plurality of channels in the first dielectric layers and connecting the first opening to the second opening, wherein the first plurality of channels is separated from the first dielectric layers by metal pipes formed on sidewalls of the first plurality of channels; and

a second die bonded to the first die.

12. The integrated circuit structure of claim 11, wherein the second die comprises a second plurality of channels configured to connect the first opening to the second opening.

13. The integrated circuit structure of claim 11, wherein the second die comprises no channel connected between the first opening and the second opening.

14. The integrated circuit structure of claim 11 further comprising a cooling agent filling the first opening, the second opening, and the first plurality of channels, wherein the first plurality of channels is configured to allow the cooling agent to flow from the first opening to the second opening.

15. An integrated circuit structure comprising:

a first die comprising;

a first semiconductor substrate;

first dielectric layers over the first semiconductor substrate;

a first interconnect structure in the first dielectric layers;

a first plurality of channels extending from inside the first semiconductor substrate to inside the first dielectric layers; and

a first dielectric film over the first interconnect structure and sealing portions of the first plurality of channels, wherein the first plurality of channels is configured to allow a fluid to flow through; and

a second die bonded to a backside of the first semiconductor substrate in the first die.

16. The integrated circuit structure of claim 15, wherein the second die further comprises:

a second semiconductor substrate;

a second interconnect structure in second dielectric layers and on a front side of the second semiconductor substrate;

a second plurality of channels extending from inside the second semiconductor substrate to inside the second dielectric layers, wherein an inner space of the second plurality of channels is connected to an inner space of the first plurality of channels; and

a second dielectric film covering the second interconnect structure and sealing portions of the second plurality of channels.

17. The integrated circuit structure of claim 15, wherein the second die further comprises:

a second semiconductor substrate; and

a second interconnect structure in second dielectric layers and on a front side of the second semiconductor substrate, wherein no channel is formed in the second dielectric layers and connected to the first plurality of channels.