Semiconductor device and method for manufacturing the same

• US 8,624,400 B2
• Filed: 07/21/2010
• Issued: 01/07/2014
• Est. Priority Date: 03/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Suzawa, Hideomi, Sasagawa, Shinya, Kurata, Motomu
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/840,442
• Publication Number:
  US 20100283105A1
• Time in Patent Office: 1,266 Days
• Field of Search: 257210-211, 257/503, 257/508, 257E33062-E33066, 257E31124-E31126, 257/E51.019
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.

Claims

1. A semiconductor device comprising:

a semiconductor layer having an opening over an insulating surface;

a first insulating layer over the semiconductor layer;

a gate electrode over the first insulating layer;

a second insulating layer over the gate electrode; and

a conductive layer over the second insulating layer,

wherein at least a part of the opening reaches the insulating surface, and

wherein the conductive layer is connected to a side surface of the semiconductor layer and a top surface of the semiconductor layer.

2. The semiconductor device according to claim 1, wherein the semiconductor layer is a single crystal silicon layer.

3. The semiconductor device according to claim 1, wherein the semiconductor layer comprise a silicide region.

4. The semiconductor device according to claim 1, wherein a thickness of the semiconductor layer is 10 to 200 nm.

5. The semiconductor device according to claim 1, wherein the conductive layer comprises tungsten.

16. The semiconductor device according to claim 1, wherein the opening reaches the insulating surface.

18. The semiconductor device according to claim 1, wherein the opening is surrounded by the semiconductor layer.

6. A semiconductor device comprising:

a semiconductor layer having an opening over an insulating surface;

a first insulating layer over the semiconductor layer;

a gate electrode over the first insulating layer;

a second insulating layer over the gate electrode; and

a conductive layer over the second insulating layer,

wherein the conductive layer is connected to the insulating surface through the opening, and

wherein the conductive layer is connected to a side surface of the semiconductor layer and a top surface of the semiconductor layer.

7. The semiconductor device according to claim 6, wherein the semiconductor layer is a single crystal silicon layer.

8. The semiconductor device according to claim 6, wherein the semiconductor layer comprise a silicide region.

9. The semiconductor device according to claim 6, wherein a thickness of the semiconductor layer is 10 to 200 nm.

10. The semiconductor device according to claim 6, wherein the conductive layer comprises tungsten.

17. The semiconductor device according to claim 6, wherein the opening reaches the insulating surface.

19. The semiconductor device according to claim 6, wherein the opening is surrounded by the semiconductor layer.

11. A semiconductor device comprising:

a semiconductor layer having a first opening over a first insulating layer , the first insulating layer having a second opening;

a second insulating layer over the semiconductor layer;

a gate electrode over the second insulating layer;

a third insulating layer over the gate electrode, the third insulating layer having a third opening; and

a conductive layer over the third insulating layer,

wherein the conductive layer is connected to a side surface of the semiconductor layer and a side surface of the silicide region.

12. The semiconductor device according to claim 11, wherein the semiconductor layer is a single crystal silicon layer.

13. The semiconductor device according to claim 11, wherein the silicide region does not overlap the second insulating film.

14. The semiconductor device according to claim 11, wherein a thickness of the semiconductor layer is 10 to 200 nm.

15. The semiconductor device according to claim 11, wherein the conductive layer comprises tungsten.

20. The semiconductor device according to claim 11,

wherein the first insulating layer is over an insulating surface,

wherein the conductive layer is connected to the insulating surface through the first opening, the second opening, and the third opening.