Test system and write wafer

• US 8,624,620 B2
• Filed: 11/22/2010
• Issued: 01/07/2014
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Komoto, Yoshio, Tokunaga, Yasuo
• Primary Examiner(s): Vazquez, Arleen M
• Assistant Examiner(s): LE, THANG XUAN
• Application Number:
  US12/952,110
• Publication Number:
  US 20110115519A1
• Time in Patent Office: 1,142 Days
• Field of Search: 32476201-76206, 324/762.05
• US Class Current: 324/762.05
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56016 Apparatus features

Abstract

A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Claims

1. A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer, comprising:

a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit;

a write wafer including a plurality of write circuits, each write circuit writing the test data to a corresponding one of the plurality of test circuits; and

a control apparatus operable to supply the test data to each write circuit;

wherein each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data.

2. The test system according to claim 1, further comprising:

a control apparatus that writes substantially similar test data to each of the plurality of write circuits in parallel.

3. The test system according to claim 1, wherein the write wafer further includes a distribution circuit for distributing the test data supplied to the distribution circuit, to each of the plurality of write circuits, and the control apparatus supplies the test data to the distribution circuit.

4. The test system according to claim 2, further comprising:

a chamber that stores a wire substrate to which the test wafer is fixed, the chamber operable to supply a signal from the test wafer to the semiconductor wafer conveyed into the chamber, and test the semiconductor wafer,

wherein the control apparatus writes the test data to each of the plurality of write circuits from outside the chamber via the wire substrate.

5. The test system according to claim 1, further comprising:

a chamber that stores a wire substrate to which the test wafer is fixed, the chamber operable to supply a signal from the test wafer to the semiconductor wafer conveyed into the chamber, and test the semiconductor wafer,

wherein for writing the test data to the test wafer, the control apparatus conveys, into the chamber, the write wafer storing thereon the test data, and writes the test data to each of the plurality of test circuits of the test wafer from the write wafer.

6. The test system according to claim 1, wherein the write wafer further includes a common storage section, the common storage section being provided in common to the plurality of write circuits, storing the test data, and supplying the test data to each of the plurality of write circuits.

7. The test system according to claim 2, further comprising:

a wafer fixing section that integrally fixes the semiconductor wafer and the test wafer, the wafer fixing section including the write wafer; and

a chamber into which the test wafer and the semiconductor wafer integrally fixed to each other by the wafer fixing section are conveyed, the chamber testing the semiconductor wafer using the test wafer.

8. The test system according to claim 7, wherein the control apparatus writes, to the write wafer for the test wafer outputted from the chamber, test data corresponding to a next test to be conducted.

9. An apparatus for writing substantially similar test data to each of a plurality of test circuits formed on a test wafer, each test circuit testing a corresponding semiconductor chip of a plurality of semiconductor chips formed on a semiconductor wafer based on the test data written to the test circuit, the apparatus comprising:

a write wafer including a plurality of write circuits corresponding to the plurality of test circuits, each write circuit writing the test data to a corresponding one of the plurality of test circuits, the test data allowing each test circuit to generate a test signal for testing a corresponding semiconductor chip of the plurality of semiconductor chips; and

a common storage section in communication with the plurality of write circuits, the common storage section storing the test data, and supplying the test data to each of the plurality of write circuits.

10. A method comprising:

receiving, at each of a plurality of write circuits included in a write wafer, test data from a control apparatus, the test data allowing each of a plurality of test circuits included in a test wafer to generate a test signal;

writing the test data from each of the plurality of write circuits to a corresponding test circuit of the plurality of test circuits; and

testing a corresponding semiconductor chip of a plurality of semiconductor chips included in a semiconductor wafer using the test signal.