Devices including phase inverters and phase mixers

• US 8,624,644 B2
• Filed: 08/01/2013
• Issued: 01/07/2014
• Est. Priority Date: 01/21/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gomm, Tyler J.
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/957,333
• Publication Number:
  US 20130314131A1
• Time in Patent Office: 159 Days
• Field of Search: 327/149, 327/158
• US Class Current: 327/158
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/14 by the use of delay lines H03K5/133 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence

Abstract

Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

Claims

1. A device, comprising:

a phase inverter configured to receive a first signal from a delay line and receive a second signal from the delay line, the phase inverter configured to provide the first signal to a first output and configured to provide an inverted second signal to a second output; and

a phase mixer coupled to the phase inverter, the phase mixer configured to provide an output clock signal having a timing that is interpolated between the timing of the first signal and the timing of the inverted second signal.

2. The device of claim 1, further comprising a delay line comprising a plurality of delay stages, wherein a delay stage of the plurality of delay stages includes a single inverting delay device, the delay line configured to provide the first signal from an input of a delay stage of the plurality of delay stages and configured to provide the second signal from an output of the delay stage.

3. The device of claim 2, wherein the single inverting delay device is a NAND gate.

4. The device of claim 2, wherein the delay line is further configured to receive a reference clock signal at a first delay stage of the plurality of delay stages, wherein the first signal and the second signal are generated from the reference clock signal.

5. The device of claim 2, wherein a delay of the delay stage is approximately equal to delays of each of the other delay stages of the plurality of delay stages.

6. The device of claim 2, wherein the delay line is configured to select the delay gate of the plurality of delay gates based on a delay control signal, wherein the delay control signal is generated based on the output signal.

7. The device of claim 1, further comprising a phase detector configured to receive a reference clock signal and receive the output clock signal, the phase detector configured to provide an output signal based on a difference in timing between the reference clock signal and the output clock signal.

8. The device of claim 7, further comprising a model delay coupled to the phase detector, the model delay configured to provide the output clock signal to the phase detector after delaying the output clock signal.

9. A device, comprising:

a phase inverter configured to provide a first signal, the first signal based on a first received signal, the phase inverter further configured to provide an inverted second signal, the inverted second signal based on a second received signal; and

a phase mixer configured to receive the first signal and the inverted second signal, the phase mixer further configured to provide a clock signal having a timing that is based on the timing of the first signal and the timing of the inverted second signal.

10. The device of claim 9, further comprising a delay line coupled to the phase inverter, the delay line configured to provide the first received signal and the second received signal, wherein a phase of the first received signal differs from a phase of the second received signal by propagation delay of a single inverting delay device.

11. The device of claim 10, wherein the single inverting delay device is a logic gate.

12. The device of claim 9 wherein the phase inverter comprises a plurality of inverters coupled in series, a first inverter of the plurality of inverters configured to receive the first received signal and a last inverter of the plurality of inverters configured to provide the first signal.

13. The device of claim 12, wherein the plurality of inverters comprises a first plurality of inverters and wherein the phase inverter further comprises a second plurality of inverters coupled in series, a first inverter of the second plurality of inverters configured to receive the second received signal and a last inverter of the second plurality of inverters configured to provide the inverted second signal.

14. The device of claim 13, wherein a number of the second plurality of inverters is different than a number of the first plurality of inverters.

15. The device of claim 14, wherein a difference between the number of the second plurality of inverters and the number of the first plurality of inverters is one.

16. The device of claim 13, wherein the second plurality of inverters includes an odd number of inverters.

17. The device of claim 13, wherein a propagation delay through the second plurality of inverters is equal to a propagation delay through the first plurality of inverters.

18. A device, comprising:

a delay line comprising a delay stage, the delay stage having a single inverting element and the delay line configured to provide first and second signals, wherein the first signal is provided from an input of the delay stage and the second signal is provided from an output of the delay stage;

a phase inverter coupled to the delay line and configured to provide a first delayed signal based on the first signal, the phase inverter further configured to provide an inverted second delayed signal based on the second signal; and

a phase mixer coupled to the phase inverter and configured to provide a clock signal having a timing that is interpolated between the timing of the first delayed signal and the timing of the inverted second delayed signal.

19. The device of claim 18, wherein a delay of the first delayed signal relative to the first signal is equal to a delay of the inverted second delayed signal relative to the second signal.

20. The device of claim 18, further comprising an exit tree coupled between the delay stage and the phase inverter, the exit tree configured to couple the input of the delay stage to the phase inverter and the output of the delay stage to the phase inverter.