Semiconductor device

• US 8,624,650 B2
• Filed: 12/20/2010
• Issued: 01/07/2014
• Est. Priority Date: 12/23/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ishii, Masato
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US12/972,623
• Publication Number:
  US 20110148497A1
• Time in Patent Office: 1,114 Days
• Field of Search: 327199-203, 327/208, 327210-212, 327/215, 327217-219
• US Class Current: 327/202
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

6. The semiconductor device according to claim 1, the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

14. The semiconductor device according to claim 1, wherein any of the first transistor and the second transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×

10¹⁴/cm³.

19. The semiconductor device according to claim 14, wherein a band gap of the oxide semiconductor layer is 2 eV or more.

24. The semiconductor device according to claim 1,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

29. The semiconductor device according to claim 1, wherein the semiconductor device is a flip-flop.

34. An electronic appliance including the semiconductor device according to claim 1.

2. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line;

wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

7. The semiconductor device according to claim 2, the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

11. The semiconductor device according to claim 2, further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

15. The semiconductor device according to claim 2, wherein any of the first transistor, the second transistor, the third transistor and the fourth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×

10¹⁴/cm³.

20. The semiconductor device according to claim 15, wherein a band gap of the oxide semiconductor layer is 2 eV or more.

25. The semiconductor device according to claim 2,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

30. The semiconductor device according to claim 2, wherein the semiconductor device is a flip-flop.

35. An electronic appliance including the semiconductor device according to claim 2.

3. A semiconductor device comprising:

a first transistor;

a second transistor;

a fifth transistor;

a sixth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the fifth transistor is electrically connected to a high voltage supply line;

wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the sixth transistor is electrically connected to a low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

8. The semiconductor device according to claim 3, the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

12. The semiconductor device according to claim 3, further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

16. The semiconductor device according to claim 3, wherein any of the first transistor, the second transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×

10¹⁴/cm³.

21. The semiconductor device according to claim 16, wherein a band gap of the oxide semiconductor layer is 2 eV or more.

26. The semiconductor device according to claim 3,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

31. The semiconductor device according to claim 3, wherein the semiconductor device is a flip-flop.

36. An electronic appliance including the semiconductor device according to claim 3.

4. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a first inverter circuit comprising first inverter transistors; and

a second inverter circuit comprising second inverter transistors,

wherein the semiconductor device is configured to input a reset signal to a gate of the third transistor and a gate of the fourth transistor;

wherein the semiconductor device is configured to input a set signal to a gate of the fifth transistor and a gate of the sixth transistor;

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one of a source and a drain of the third transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the third transistor is electrically connected to a low voltage supply line;

wherein one of a source and a drain of the fourth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the fourth transistor is electrically connected to a high voltage supply line;

wherein one of a source and a drain of the fifth transistor is electrically connected to the input of the first inverter circuit;

wherein the other of the source and the drain of the fifth transistor is electrically connected to the high voltage supply line;

wherein one of a source and a drain of the sixth transistor is electrically connected to the input of the second inverter circuit;

wherein the other of the source and the drain of the sixth transistor is electrically connected to the low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

9. The semiconductor device according to claim 4, the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

13. The semiconductor device according to claim 4, further comprising:

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to the low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit; and

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line.

17. The semiconductor device according to claim 4, wherein any of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×

10¹⁴/cm³.

22. The semiconductor device according to claim 17, wherein a band gap of the oxide semiconductor layer is 2 eV or more.

27. The semiconductor device according to claim 4,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

32. The semiconductor device according to claim 4, wherein the semiconductor device is a flip-flop.

37. An electronic appliance including the semiconductor device according to claim 4.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a first inverter circuit comprising first inverter transistors;

a second inverter circuit comprising second inverter transistors,

a first capacitor comprising a first pair of electrodes; and

a second capacitor comprising a second pair of electrodes,

wherein one of a source and a drain of the first transistor is electrically connected to a first wiring;

wherein the other of the source and the drain of the first transistor is electrically connected to an input of the first inverter circuit;

wherein an output of the first inverter circuit is electrically connected to one of a source and a drain of the second transistor;

wherein the other of the source and the drain of the second transistor is electrically connected to an input of the second inverter circuit;

wherein an output of the second inverter circuit is electrically connected to a second wiring;

wherein one electrode of the first capacitor is electrically connected to the input of the first inverter circuit;

wherein the other electrode of the first capacitor is electrically connected to a low voltage supply line;

wherein one electrode of the second capacitor is electrically connected to the input of the second inverter circuit;

wherein the other electrode of the second capacitor is electrically connected to the low voltage supply line;

wherein each of the first transistor and the second transistor comprises a channel formation region in an oxide semiconductor layer; and

wherein at least one of the first inverter transistors and one of the second inverter transistors comprise a channel formation region in a material other than an oxide semiconductor material.

10. The semiconductor device according to claim 5, the semiconductor device being further configured to input an inverted clock signal to a gate of the first transistor and a clock signal to a gate of the second transistor.

18. The semiconductor device according to claim 5, wherein any of the first transistor and the second transistor includes an oxide semiconductor layer in which a carrier concentration is less than 1×

10¹⁴/cm³.

23. The semiconductor device according to claim 18, wherein a band gap of the oxide semiconductor layer is 2 eV or more.

28. The semiconductor device according to claim 5,

wherein the first inverter circuit and the second inverter circuit each are a CMOS inverter circuit comprising at least a p-channel transistor with a channel formation region formed in silicon.

33. The semiconductor device according to claim 5, wherein the semiconductor device is a flip-flop.

38. An electronic appliance including the semiconductor device according to claim 5.