Memory device having memory cells with write assist functionality

• US 8,625,333 B2
• Filed: 02/22/2011
• Issued: 01/07/2014
• Est. Priority Date: 02/22/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Rao, Setti Shanmukheswara, Rachamadugu, Vinod
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huang, Min
• Application Number:
  US13/031,798
• Publication Number:
  US 20120212996A1
• Time in Patent Office: 1,050 Days
• Field of Search: 365/154
• US Class Current: 365/154
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

Claims

1. A memory device comprising:

a memory array comprising a plurality of memory cells;

at least a given one of the memory cells comprising;

a pair of cross-coupled inverters; and

write assist circuitry;

the write assist circuitry comprising;

first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and

second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell;

wherein the first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline of the memory device, and the second switching circuitry being controlled using the wordline and a complemented bitline of the memory device.

2. The memory device of claim 1 wherein the wordline comprises a write wordline having a corresponding read wordline and the uncomplemented and complemented bitlines comprise respective uncomplemented and complemented write bitlines having respective corresponding uncomplemented and complemented read bitlines.

3. The memory device of claim 1 wherein first and second write assist transistors of the first switching circuitry have gate terminals coupled to the wordline and the uncomplemented bitline, respectively, and first and second write assist transistors of the second switching circuitry have gate terminals coupled to the wordline and the complemented bitline, respectively.

4. The memory device of claim 1 wherein the first switching circuitry is coupled between a supply node of a pull-up device of the first inverter and an upper power supply node of the memory cell, the second switching circuitry is coupled between a supply node of a pull-up device of the second inverter and the upper power supply node of the memory cell, and the first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the pull-up devices is connected to the upper power supply node while the supply node of the other pull-up device is not connected to the upper power supply node but is instead permitted to float.

5. The memory device of claim 4 wherein the pull-up devices of the first and second inverters comprise respective pull-up transistors and the first and second inverters further comprise respective pull-down transistors.

6. The memory device of claim 5 wherein source terminals of the pull-up transistors are coupled to respective ones of the device supply nodes, drain terminals of the pull-up transistors are coupled to respective drain terminals of the pull-down transistors at respective first and second internal data nodes of the cross-coupled inverters, source terminals of the pull-down transistors are coupled to ground potential, and the first inverter is cross-coupled to the second inverter by coupling gates of the pull-up and pull-down transistors of the first inverter to the second internal data node and gates of the pull-up and pull-down transistors of the second inverter to the first internal data node.

7. The memory device of claim 1 wherein:

the first switching circuitry comprises a first plurality of write assist transistors connected in parallel with one another with their source and drain terminals coupled between the supply node of the device of the first inverter and the supply node of the memory cell; and

the second switching circuitry comprises a second plurality of write assist transistors connected in parallel with one another with their source and drain terminals coupled between the supply node of the device of the second inverter and the supply node of the memory cell;

wherein gate terminals of a first one of the first plurality of write assist transistors and a first one of the second plurality of write assist transistors are coupled to the wordline; and

wherein gate terminals of a second one of the first plurality of write assist transistors and a second one of the second plurality of write assist transistors are coupled to respective uncomplemented and complemented bitlines.

8. The memory device of claim 7 wherein during a write operation of the memory cell the first and second write assist transistors of the first plurality of write assist transistors are in their respective off states, the first write assist transistor of the second plurality of write assist transistors is in its off state, and the second write assist transistor of the second plurality of write assist transistors is in its on state, such that the supply node of the device of the second inverter is connected to the supply node of the memory cell by the second write assist transistor of the second plurality of write assist transistors, while the supply node of the device of the first inverter is disconnected from the supply node of the memory cell by the first and second write assist transistors of the first plurality of write assist transistors.

9. The memory device of claim 1 wherein the memory cell further comprises pass gate circuitry, the pass gate circuitry comprising:

third switching circuitry coupled between a first internal data node of the cross-coupled inverters and a lower supply node of the memory cell;

fourth switching circuitry coupled between a second internal data node of the cross-coupled inverters and the lower supply node of the memory cell;

wherein the third and fourth switching circuitry are separately controlled, with the third switching circuitry being controlled using the wordline and the uncomplemented bitline, and the fourth switching circuitry being controlled using the wordline and the complemented bitline.

10. The memory device of claim 9 wherein first and second pass gate transistors of the third switching circuitry have gate terminals coupled to the wordline and the uncomplemented bitline, respectively, and first and second pass gate transistors of the fourth switching circuitry have gate terminals coupled to the wordline and the complemented bitline, respectively.

11. The memory device of claim 10 wherein:

the first pass gate transistor of the third switching circuitry has its drain terminal coupled to the first internal data node and its source terminal coupled to the drain terminal of the second pass gate transistor of the third switching circuitry;

the second pass gate transistor of the third switching circuitry has its source terminal coupled to the lower supply node of the memory cell;

the first pass gate transistor of the fourth switching circuitry has its drain terminal coupled to the second internal data node and its source terminal coupled to the drain terminal of the second pass gate transistor of the fourth switching circuitry; and

the second pass gate transistor of the fourth switching circuitry has its source terminal coupled to the lower supply node of the memory cell.

12. The memory device of claim 11 wherein during a write operation of the memory cell the first and second pass gate transistors of the third switching circuitry are in their respective on states so as to connect the first internal data node to the lower supply node of the memory cell while at least the second pass gate transistor of the fourth switching circuitry is in its off state such that the second internal data node is not connected to the lower supply node of the memory cell.

13. An integrated circuit comprising the memory device of claim 1.

14. A processing device comprising the memory device of claim 1.

15. A method comprising:

providing a memory cell comprising a pair of cross-coupled inverters, write assist circuitry and pass gate circuitry; and

during a write operation of the memory cell;

configuring the write assist circuitry to connect an upper supply node of a device of one of the inverters to an upper supply node of the memory cell responsive to a wordline signal and one of an uncomplemented bitline signal and a complemented bitline signal while an upper supply node of a device of another one of the inverters is not connected to the upper supply node of the memory cell responsive to the wordline signal and the other of the uncomplemented bitline signal and the complemented bitline signal; and

configuring the pass gate circuitry to connect one of a first internal data node and a second internal data node of the cross-coupled inverters to a lower supply node of the memory cell while the other of the first internal data node and the second internal data node of the cross-coupled inverters is not connected to the lower supply node of the memory cell;

wherein configuring the write assist circuitry comprises;

configuring first switching circuitry coupled between the upper supply node of the device of one of the inverters and the upper supply node of the memory cell using the wordline signal and the uncomplemented bitline signal; and

configuring second switching circuitry coupled between the upper supply node of the device of the other one of the inverters and the upper supply node of the memory cell using the wordline signal and the complemented bitline signal.

16. The method of claim 15 wherein the configuring steps further comprise:

applying a write wordline signal to first transistors in each of first and second pluralities of transistors of the write assist circuitry;

applying an uncomplemented write bitline signal to a second transistor in the first plurality of transistors of the write assist circuitry;

applying a complemented write bitline signal to a second transistor in the second plurality of transistors of the write assist circuitry;

applying the write wordline signal to first transistors in each of first and second pluralities of transistors of the pass gate circuitry;

applying the uncomplemented write bitline signal to a second transistor in the first plurality of transistors of the pass gate circuitry; and

applying the complemented write bitline signal to a second transistor in the second plurality of transistors of the pass gate circuitry.

17. A memory cell comprising:

a pair of cross-coupled inverters; and

write assist circuitry;

the write assist circuitry comprising;

first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell; and

second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell;

wherein the first and second switching circuitry are separately controlled, with the first switching circuitry being controlled using a wordline and an uncomplemented bitline associated with the memory cell, and the second switching circuitry being controlled using the wordline and a complemented bitline associated with the memory cell.

18. The memory cell of claim 17 wherein:

the first switching circuitry comprises a first plurality of transistors connected in parallel with one another with their source and drain terminals coupled between the supply node of the device of the first inverter and the supply node of the memory cell; and

the second switching circuitry comprises a second plurality of transistors connected in parallel with one another with their source and drain terminals coupled between the supply node of the device of the second inverter and the supply node of the memory cell;

wherein gate terminals of a first one of the first plurality of transistors and a first one of the second plurality of transistors are coupled to the wordline; and

wherein gate terminals of a second one of the first plurality of transistors and a second one of the second plurality of transistors are coupled to the uncomplemented and complemented bitlines, respectively.

19. The memory cell of claim 17 wherein the memory cell further comprises pass gate circuitry, the pass gate circuitry comprising:

third switching circuitry coupled between a first internal data node of the cross-coupled inverters and a lower supply node of the memory cell;

fourth switching circuitry coupled between a second internal data node of the cross-coupled inverters and the lower supply node of the memory cell;

wherein the third and fourth switching circuitry are separately controlled, with the third switching circuitry being controlled using the wordline and the uncomplemented bitline, and the fourth switching circuitry being controlled using the wordline and the complemented bitline, respectively.

20. The memory cell of claim 19 wherein:

first and second pass gate transistors of the third switching circuitry have gate terminals coupled to the wordline and the uncomplemented bitline, respectively;

first and second pass gate transistors of the fourth switching circuitry have gate terminals coupled to the wordline and the complemented bitline, respectively;

the first pass gate transistor of the third switching circuitry has its drain terminal coupled to the first internal data node and its source terminal coupled to the drain terminal of the second pass gate transistor of the third switching circuitry;

the second pass gate transistor of the third switching circuitry has its source terminal coupled to the lower supply node of the memory cell;

the first pass gate transistor of the fourth switching circuitry has its drain terminal coupled to the second internal data node and its source terminal coupled to the drain terminal of the second pass gate transistor of the fourth switching circuitry; and

the second pass gate transistor of the fourth switching circuitry has its source terminal coupled to the lower supply node of the memory cell.