Multi-cell per memory-bit circuit and method

• US 8,625,339 B2
• Filed: 04/11/2011
• Issued: 01/07/2014
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: Samsung Semiconductor Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Grandis, Inc. (Samsung Electronics Co. Ltd.)
• Inventors: Ong, Adrian E.
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/083,854
• Publication Number:
  US 20120257448A1
• Time in Patent Office: 1,002 Days
• Field of Search: 365/171
• US Class Current: 365/171
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A write circuit is adapted to provide a same logical bit to each of a multitude of memory cells for storage. Each of the multitude of memory cells stores either the bit or a complement of the bit in response to the write circuit. A read circuit is adapted to receive the bits stored in the multitude of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule. The predefined rule may be characterized by a statistical mode of the bits stored in the plurality of memory cells. Storage errors in a minority of the multitude of memory cells may be ignored at the cost of lower memory density. The predefined rule may be characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

Claims

1. A memory circuit comprising:

a write circuit adapted to provide a same bit to each of a plurality of memory cells for storage, each of the plurality of memory cells storing either the bit or a complement of the bit in response; and

a read circuit adapted to receive the bits stored in the plurality of memory cells and to generate an output value defined by the stored bits in accordance with a predefined rule,

wherein the predefined rule is characterized by a first weight assigned to bits 1 and a second weight assigned to bits 0.

2. The memory circuit of claim 1 wherein the predefined rule is characterized by a statistical mode of the bits stored in the plurality of memory cells.

3. The memory circuit of claim 1 further comprising:

a word-line; and

a plurality of columns wherein each of the plurality of memory cells is coupled to the word-line and to corresponding ones of the plurality of columns.

4. The memory circuit of claim 3 wherein each of the plurality of columns includes a first signal line and a second signal line, and one of the plurality of memory cells comprises (i) a first current carrying terminal coupled to the first signal line, (ii) a second current carrying terminal coupled to the second signal line and (iii) a control terminal coupled to the word-line.

5. The memory circuit of claim 4 wherein one of the plurality of memory cells further comprises:

a magnetic tunnel junction having a first terminal coupled to the first current carrying terminal of one of the plurality of memory cells; and

a first transistor having (i) a first current carrying terminal coupled to the second current carrying terminal of one of the plurality of memory cells, (ii) a gate terminal coupled to the control terminal of one of the plurality of memory cells and (iii) a second current carrying terminal coupled to a second terminal of said magnetic tunnel junction.

6. The memory circuit of claim 1 wherein one of said plurality of memory cells is a DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PRAM, MRAM, ReRAM, STT-MRAM, or ReRAM (resistive RAM) cell.

7. The memory circuit of claim 1 wherein the output value is generated by one of a plurality of selectable logic circuits and the selection of the logic circuit is made by a program input.

8. The memory circuit of claim 7 wherein the non-selected ones of the plurality of selectable logic circuits are powered down.

9. The memory circuit of claim 1 further comprising a plurality of sense amplifiers wherein each of the plurality of memory cells is coupled to corresponding ones of the plurality of sense amplifiers and the output of each of the plurality of sense amplifiers is coupled to the input of a logic circuit.

10. The memory circuit of claim 9 wherein (i) each of the plurality of memory cells is coupled to a first current carrying terminal of a corresponding first transistor, (ii) a second current carrying terminal of the corresponding first transistor is coupled to the input of the corresponding ones of the plurality of sense amplifiers and (iii) a control terminal of each of the corresponding first transistors is coupled to a first signal line.

11. The memory circuit of claim 1 wherein the plurality of memory cells are adjacently located.

12. The memory circuit of claim 1 wherein the plurality of memory cells are non-adjacently located.

13. The memory circuit of claim 1, further comprising:

a plurality of groups of c physical cells, wherein c bit values associated with the c physical cells of each group form a logical bit;

a plurality of groups of c n-channel select transistors, each of the c n-channel select transistors of each group being coupled to a corresponding one of the c physical cells; and

a program bit register weight comparator coupled to the plurality of groups of c n-channel select transistors, the program bit register weight comparator being adapted to generate the predefined rule characterized by the first weight assigned to the bits 1 and the second weight assigned to the bits 0.

14. The memory circuit of claim 13, wherein the program bit register weight comparator further comprises:

a program bit register; and

a plurality of d weight comparators coupled to the program bit register, each of the weight comparators adapted to receive a corresponding one of d signals from the program bit register, and adapted to receive the c bit values associated with the c physical cells.

15. The memory circuit of claim 14, wherein each of the plurality of d weight comparators further comprises:

1st through cth logic gates, each of the 1st through cth logic gates adapted to receive at least one inverted bit value from among the c bit values associated with the c physical cells, and adapted to receive at least one non-inverted bit value from among the c bit values associated with the c physical cells;

an input logic gate adapted to receive non-inverted bit values from among the c bit values associated with the c physical cells; and

an output logic gate coupled to the 1st through cth logic gates and to the input logic gate, and adapted to transmit a weighted output.

16. A method of operating a memory circuit, the method comprising:

providing a same bit to each of a plurality of memory cells, each of the plurality of memory cells storing either the bit or a complement of the bit in response;

receiving the bits stored in the plurality of memory cells;

generating an output value defined by the stored bits in accordance with a predefined rule; and

characterizing the predefined rule by a first weight assigned to bits 1 and a second weight assigned to bits 0.

17. The method of claim 16 further comprising characterizing the predefined rule by a statistical mode of the bits stored in the plurality of memory cells.

18. The method of claim 16 further comprising:

coupling the plurality of memory cells to a word-line and to corresponding ones of a plurality of columns.

19. The method of claim 18 further comprising:

forming each of the plurality of columns from a first signal line and a second signal line;

coupling a first current carrying terminal of one of the plurality of memory cells to the first signal line;

coupling a second current carrying terminal of one of the plurality of memory cells to the second signal line; and

coupling a control terminal of one of the plurality of memory cells to the word-line.

20. The memory circuit of claim 19 further comprising;

coupling a first terminal of a magnetic tunnel junction to the first current carrying terminal of one of the plurality of memory cells;

coupling a first current carrying terminal of a first transistor to the second current carrying terminal of one of the plurality of memory cells;

coupling a gate terminal of the first transistor to the control terminal of one of the plurality of memory cells; and

coupling a second current carrying terminal of the first transistor to a second terminal of the magnetic tunnel junction.

21. The method of claim 16 further comprising providing one of said plurality of memory cells as a DRAM, SRAM, ROM, PROM, EEPROM, FLASH, FeRAM, PRAM, MRAM, STT-MRAM, or ReRAM (resistive RAM) cell.

22. The method of claim 16 further comprising generating the output value by selecting one of a plurality of selectable logic circuits and selecting the logic circuit by a program input.

23. The method of claim 22 further comprising powering down the non-selected ones of the plurality of selectable logic circuits.

24. The method of claim 16 further comprising:

coupling each of the plurality of memory cells to corresponding ones of a plurality of sense amplifiers; and

coupling the output of each of the plurality of sense amplifiers to the input of a logic circuit.

25. The method of claim 24 further comprising:

coupling each of the plurality of memory cells to a first current carrying terminal of a corresponding first transistor; and

coupling a second current carrying terminal of the corresponding first transistor to the input of the corresponding ones of the plurality of sense amplifiers;

coupling a control terminal of each of the corresponding first transistors to a first signal line.

26. The method of claim 16 further comprising locating the plurality of memory cells adjacently.

27. The method of claim 16 further comprising locating the plurality of memory cells non-adjacently.