Memory component with terminated and unterminated signaling inputs

• US 8,625,371 B2
• Filed: 06/21/2013
• Issued: 01/07/2014
• Est. Priority Date: 04/24/2001
• Status: Expired due to Fees

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/923,634
• Publication Number:
  US 20130279278A1
• Time in Patent Office: 200 Days
• Field of Search: 365/194, 365/191, 365/193, 365/189.04
• US Class Current: 365/194
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

Claims

1. A memory component comprising:

a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals, a strobe input and a clock input, each to be coupled to a respective external signaling link;

data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write date bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O;

CA circuitry to sample the CA signals at the CA input, the sampling of the CA signals being timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively; and

closed-loop clock generation circuitry coupled to receive the second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

2. The memory component of claim 1 wherein the signaling interface further has an on-die terminated write mask input to be coupled to an external write-mask signal link.

3. The memory component of claim 2 further comprising input circuitry to sample write mask signals at the write mask input, the sampling of the write mask signals being timed by the strobe signal, each write mask signal indicating whether a corresponding set of the write data bits sampled by the data I/O circuitry are to be stored within the memory component.

4. The memory component of claim 1 wherein the CA circuitry samples the CA signals at a first signaling rate and the data I/O circuitry samples the write data bits at a second signaling rate, the second signaling rate being twice the first signaling rate.

5. The memory component of claim 4 wherein the second signaling rate is twice the frequency of the second clock signal.

6. The memory component of claim 1 wherein the CA circuitry samples the CA signals in response to every other transition of the second clock signal and the data I/O circuitry samples the write data bits in response to both rising-edge and falling-edge transitions of the strobe signal.

7. The memory component of claim 1 wherein the closed-loop clock generation circuitry to generate the first clock signal with the phase that establishes the alignment between the leading edge of the bit time for each read data bit and the respective transition of the second clock signal comprises a phase comparator coupled to receive the second clock signal.

8. The memory component of claim 1 wherein the on-die-terminated data I/O comprises (i) a plurality of data input/output nodes, each to be coupled to a respective constituent signaling line of the external signaling link, and (ii) a plurality of on-die terminations coupled respectively to the plurality of data input/output nodes, each to enable termination of the respective constituent signaling line.

9. The memory component of claim 8 wherein each of the plurality of on-die terminations comprises a transistor device.

10. A memory component comprising:

a signaling interface having an on-die terminated data input/output (I/O), an on-die terminated write mask input, an unterminated input to receive command/address (CA) signals, a strobe input and a clock input, each to be coupled to a respective external signaling link, the on-die terminated data I/O including (i) a plurality of data I/O nodes, each to be coupled to a respective constituent signaling line of the external signaling link, and (ii) a plurality of on-die terminations coupled respectively to the plurality of data I/O nodes, each of the on-die terminations to enable termination of the respective constituent signaling line;

data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O;

CA circuitry to sample CA signals at the CA input, the sampling of the CA signals being timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively;

mask input circuitry to sample write mask signals at the write mask input timed by the strobe signal, each write mask signal indicating whether a corresponding set of the write data bits sampled by the data I/O circuitry are to be stored within the memory component; and

closed-loop clock generation circuitry coupled to receive the second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

11. A method of operation within a memory component, the method comprising:

receiving a first clock signal via a clock input;

sampling command/address (CA) signals at an unterminated CA input synchronously with respect to the first clock signal;

in response to CA signals that indicate memory write operations, sampling write data bits received at an on-die terminated data input/output (I/O), the sampling of the write data bits being timed by a strobe signal received via a strobe input;

in response to CA signals that indicate memory read operations, transmitting, via the data I/O, read data bits timed by a second clock signal, each of the read data bits being valid for a respective bit time at the data I/O; and

generating the second clock signal with a phase that establishes, at a signaling interface constituted in part by the data I/O and the clock input, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the first clock signal.

12. The method of claim 11 further comprising sampling write mask signals at a write mask input, the sampling of the write mask signals being timed by the strobe signal, each write mask signal indicating whether a corresponding set of the write data bits sampled at the data input are to be stored within the memory component.

13. The method of claim 11 wherein sampling CA signals comprises sampling the CA signals at a first rate and wherein sampling write data bits comprises sampling the write data bits at a second rate, the second rate being twice the first rate.

14. The method of claim 13 wherein the second rate is twice the frequency of the first clock signal.

15. The method of claim 14 wherein sampling CA signals timed by the first clock signal comprises sampling the CA signals in response to every other transition of the first clock signal, and wherein sampling write data bits timed by the strobe signal comprises sampling the write data bits in response to both rising-edge and falling-edge transitions of the strobe signal.

16. A memory module comprising:

a circuit board;

a termination structure disposed on the circuit board;

a command/address (CA) signal path that extends from an edge of the circuit board to the termination structure; and

a plurality of memory components disposed on the circuit board and coupled to the CA signal path at respective locations between the edge of the circuit board and the termination structure, each memory component of the plurality of memory components including;

a signaling interface having a CA input, a data input/output (I/O), a strobe input and a clock input, the CA input being coupled to the CA signal path;

data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O;

CA circuitry to sample CA signals at the CA input, the sampling of the CA signals being timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively;

closed-loop clock generation circuitry coupled to receive a second clock signal via the clock input and to generate the first clock signal with a phase that establishes, at the signaling interface, an alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal; and

an on-die termination coupled to the data I/O.

17. The memory module of claim 16 further comprising a clock signal path to convey the second clock signal, the clock signal path extending from the circuit board edge and coupled to the clock input of each of the memory components such that the second clock signal arrives at the clock inputs of respective memory components at progressively later times corresponding to times at which the CA signals arrive at the CA inputs of the memory components.

18. The memory module of claim 16 further comprising:

a plurality of data signal paths, each extending from the circuit board edge to the data I/O of a respective one of the memory components and each including a first plurality of data signal conductors to convey write data values and read data values constituted by the write data bits and read data bits, respectively; and

a plurality of strobe signal paths that extend from the circuit board edge to respective strobe inputs of the memory components.

19. The memory module of claim 18 wherein each memory component further includes a write mask input to receive a mask signal that indicates whether a corresponding set of the write data bits sampled by the data I/O circuitry are to be stored within the memory component, and wherein the memory module further comprises at least one mask signal conductor to convey the write mask signal.

20. The memory module of claim 16 wherein the CA circuitry within each memory component samples the CA signals at a first signaling rate and the data I/O circuitry within each memory component samples the write data bits at a second signaling rate, the second signaling rate being twice the first signaling rate.