Semiconductor memory device and method of operation the same

• US 8,625,376 B2
• Filed: 11/01/2011
• Issued: 01/07/2014
• Est. Priority Date: 11/02/2010
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Jung, Min Joong, Lee, Wan Seob
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/286,595
• Publication Number:
  US 20120281488A1
• Time in Patent Office: 798 Days
• Field of Search: 365/222
• US Class Current: 365/222
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.

Claims

1. A semiconductor memory device, comprising:

a first plane and a second plane each comprising a plurality of memory cells;

a first page buffer group comprising a plurality of page buffers for temporarily storing data to be stored in the memory cells of the first plane and data read from the memory cells of the first plane;

a second page buffer group comprising a plurality of page buffers for temporarily storing data to be stored in the memory cells of the second plane and data read from the memory cells of the second plane;

a data transfer circuit configured to transfer first data, outputted from the first page buffer group, to the second page buffer group to store the first data, stored in the memory cells of the first plane, in the second plane and to transfer second data, outputted from the second page buffer group, to the first page buffer group to store the second data, stored in the memory cells of the second plane, in the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed;

a column selector configured to select which page buffers of the first and the second page buffer groups to output in response to a column address signal,

wherein the column selector comprises a column address counter configured to increase the column address when outputting the data stored in the first or the second page buffer group to the data transfer circuit.

2. The semiconductor memory device of claim 1, further comprising an operation circuit group for supplying an operation voltage to the first and the second plane to store data from the first and the second page buffer groups in the memory cells of the first and the second planes and to output data in the memory cells of the first and the second planes to the first and the second page buffer groups.

3. The semiconductor memory device of claim 1, wherein the data transfer circuit comprises:

a first data transfer unit configured to transfer the first data of the first page buffer group to the I/O circuit when a read operation is performed; and

a second data transfer unit configured to transfer the second data of the second page buffer group to the I/O circuit when a read operation is performed,

wherein when the first data of the first page buffer group is transferred to the second page buffer group or the second data of the second page buffer group is transferred to the first page buffer group, a data transfer path is formed between the first data transfer unit and the second data transfer unit to transfer the first data or the second data between the first page buffer group and the second page buffer group.

4. The semiconductor memory device of claim 3, wherein the first data transfer unit comprises a first switching element coupled between the first page buffer group and the I/O circuit.

5. The semiconductor memory device of claim 4, wherein the second data transfer unit comprises a second switching element coupled between the second page buffer group and the I/O circuit.

6. The semiconductor memory device of claim 5, wherein the data transfer circuit further comprises a third data transfer unit for transferring the first data of the first data transfer unit or the second data of the second data transfer unit to the I/O circuit.

7. The semiconductor memory device of claim 6, wherein the third data transfer unit further comprises a third switching element coupled between the first data transfer unit and the I/O circuit and between the second data transfer unit and the I/O circuit.

8. The semiconductor memory device of claim 7, wherein the third data transfer unit blocks a connection between the first data transfer unit and the I/O circuit and between the second data transfer unit and the I/O circuit when the first data of the memory cells of the first plane is transferred to the second plane and when the second data of the memory cells of the second plane is transferred to the first plane in the copyback operation.

9. The semiconductor memory device of claim 1, wherein the data transfer circuit is configured to transfer the first data and the second data in response to a data input signal or a data output signal that is generated using a read enable clock signal.

10. A method of operating a semiconductor memory device, comprising:

storing data, stored in memory cells of a first plane, in page buffers of the first plane in response to a read command;

transferring the data to a data line while increasing a page column address of the first plane in response to a data output signal generated using a read enable clock signal;

storing the data to page buffers of a second plane while increasing a page column address of the second plane in response a data input signal generated using the read enable clock signal; and

storing the data of the page buffers of the second plane in the memory cells of the second plane in response to a program command,

wherein the page column address of the first and the second plane is increased by a column address counter included in a column selector configured to select which page buffers of the first and the second planes when transferring the data to the data line and storing the data to the page buffers of the second plane.

11. The method of claim 10, wherein the data line is a global data line.

12. The method of claim 11, wherein when storing the data of the global data line in the page buffers of the second plane, a connection between the global data line and a circuit outside the semiconductor memory device is blocked.