Memory word line boost using thin dielectric capacitor

• US 8,625,383 B2
• Filed: 01/08/2013
• Issued: 01/07/2014
• Est. Priority Date: 11/18/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Hung-Chang, Chih, Yue-Der
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/736,501
• Publication Number:
  US 20130121088A1
• Time in Patent Office: 364 Days
• Field of Search: 365/230.06, 365/189.09, 365/149
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A memory including a boost circuit configured to supply a voltage higher than a supply voltage to a word line. The boost circuit includes a first capacitor having a first capacitor dielectric thickness. The boost circuit further includes a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

Claims

1. A memory, comprising:

a boost circuit configured to supply a voltage higher than a supply voltage to a word line, the boost circuit including;

a first capacitor having a first capacitor dielectric thickness; and

a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

2. The memory of claim 1, wherein the transmission gate comprises an n-well device.

3. The memory of claim 2, wherein the boost circuit further includes a second capacitor having a second capacitor dielectric thickness greater than the first capacitor dielectric thickness, the second capacitor configured to provide a voltage higher than the supply voltage to a bulk of the n-well device.

4. The memory of claim 2, wherein an area of the first capacitor is 25% of an area of the n-well device.

5. The memory of claim 1, wherein the boost circuit further includes:

a pulse generator configured to generate a first pulse;

a delay buffer configured to delay the first pulse by a delay time; and

a second capacitor configured to boost a voltage of a bulk in the transmission gate, wherein the first capacitor is configured to receive the first pulse delayed by the delay time and the second capacitor is configured to receive the first pulse.

6. The memory of claim 1, further comprising a second capacitor configured to boost a voltage of a bulk in the transmission gate, wherein the second capacitor is configured to be disconnected from the word line during a first operation of the memory.

7. The memory of claim 6, wherein the second capacitor is configured to be connected to the word line during a second operation of the memory.

8. The memory of claim 1, wherein the transmission gate is configured to connect the first capacitor to the word line during a first operation of the memory.

9. The memory of claim 8, wherein the transmission gate is configured to disconnect the first capacitor from the word line during a second operation of the memory.

10. A method for boosting a word line of a memory, comprising:

charging a first capacitor having a first capacitor dielectric thickness in a boost circuit to a power supply voltage; and

boosting a voltage level of the word line to a voltage that is higher than the power supply voltage through a transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness.

11. The method of claim 10, wherein charging a first capacitor comprise charging a first capacitor having a first area, and boosting the voltage level through the transmission gate comprises booting the voltage level through the transmission gate having an n-well device having a second area, and the first area is 25% of the second area.

12. The method of claim 10, wherein boosting the voltage level through the transmission gate comprises providing a voltage higher than the supply voltage to a bulk of the transmission gate using a second capacitor having a second capacitor dielectric thickness greater than the first capacitor dielectric thickness.

13. The method of claim 10, further comprising:

generating a first pulse using a pulse generator;

delaying the first pulse by a delay time using a delay buffer;

supplying the first pulse to a second capacitor configured to boost a voltage of a bulk in the transmission gate; and

supplying the delayed first pulse to the first capacitor.

14. The method of claim 10, further comprising disconnecting a second capacitor configured to boost a voltage of a bulk in the transmission gate from the word line.

15. The method of claim 10, further comprising connecting a second capacitor configured to boost a voltage of a bulk of the transmission gate to the word line.

16. The method of claim 10, further comprising connecting the first capacitor to the word line using the transmission gate.

17. The method of claim 10, further comprising disconnecting the first capacitor from the word line using the transmission gate.

18. A memory, comprising:

a boost circuit including;

a first capacitor having a first capacitor dielectric thickness;

a transmission gate coupled to a word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness;

a second capacitor configured to boost a voltage of a bulk of the transmission gate, the second capacitor having a second capacitor dielectric thickness that is greater than the first capacitor dielectric thickness;

wherein the first capacitor and the second capacitor are configured to be connected to a ground during a first operation of the memory.

19. The memory of claim 18, wherein the boost circuit further includes:

a pulse generator configured to generate a pulse; and

a delay buffer configured to delay the pulse by a delay time,

wherein the first capacitor is configured to receive the pulse delayed by the delay time during a second operation of the memory, and the second capacitor is configured to receive the pulse during the second operation of the memory.

20. The memory of claim 18, further comprising a word line, wherein the first capacitor is configured to be disconnected from the word line during the first operation of the memory, and the second capacitor is configured to be connected to the word line during the first operation of the memory.